JPS5550764A - Digital signal receiver - Google Patents

Digital signal receiver

Info

Publication number
JPS5550764A
JPS5550764A JP12339878A JP12339878A JPS5550764A JP S5550764 A JPS5550764 A JP S5550764A JP 12339878 A JP12339878 A JP 12339878A JP 12339878 A JP12339878 A JP 12339878A JP S5550764 A JPS5550764 A JP S5550764A
Authority
JP
Japan
Prior art keywords
signal
circuit
inputted
control
threshold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP12339878A
Other languages
Japanese (ja)
Other versions
JPS589626B2 (en
Inventor
Hitoshi Imagawa
Masao Iida
Akira Fukui
Kojiro Sakurai
Kensaku Fujii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Fujitsu Ltd
Hitachi Ltd
NEC Corp
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Hitachi Ltd, NEC Corp, Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd, Nippon Electric Co Ltd filed Critical Fujitsu Ltd
Priority to JP53123398A priority Critical patent/JPS589626B2/en
Publication of JPS5550764A publication Critical patent/JPS5550764A/en
Publication of JPS589626B2 publication Critical patent/JPS589626B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q1/00—Details of selecting apparatus or arrangements
    • H04Q1/18—Electrical details
    • H04Q1/30—Signalling arrangements; Manipulation of signalling currents
    • H04Q1/44—Signalling arrangements; Manipulation of signalling currents using alternate current
    • H04Q1/444—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies
    • H04Q1/45—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling
    • H04Q1/457—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals
    • H04Q1/4575—Signalling arrangements; Manipulation of signalling currents using alternate current with voice-band signalling frequencies using multi-frequency signalling with conversion of multifrequency signals into digital signals which are transmitted in digital form

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To receive MF signal and CS signal simultaneously by providing a control circuit in MF signal receiver in the receiving time shared multiplex signal of the pulse code modulated multifrequency (MF) signal and a single frequency (CS) signal. CONSTITUTION:The time shared multiplex signal of the pulse code modulated MF signal and CS signal is multiplied by the output of the wind function generator 13 by the multiplier 12 and inputted into the temporary store circuit 14' variable in store time. The output signal of the circuit 14' is inputted discretely to Fourier conversion circuit 15, integrated 20, 21, converted into absolute values 22, 23, added 24, and inputted to the digital comparison judging circuit 25. In the circuit 25, the signal is compared with the threshold from the varible level threshold generating curcuit 26' and the input exceeding the threshold is judged to an aimed frequency and the result thereof is outputted through the storage circuit 27. The change of the level of the circuit 26' due to the change in store time of CS signal and MF signal and the difference in the input level is controlled by the control circuit 11. Simultaneously, the control signal is impressed to the sine wave and cosine wave generating circuit 18, 19 synchronously with the control of the circuit 14'.
JP53123398A 1978-10-06 1978-10-06 digital signal receiver Expired JPS589626B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53123398A JPS589626B2 (en) 1978-10-06 1978-10-06 digital signal receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53123398A JPS589626B2 (en) 1978-10-06 1978-10-06 digital signal receiver

Publications (2)

Publication Number Publication Date
JPS5550764A true JPS5550764A (en) 1980-04-12
JPS589626B2 JPS589626B2 (en) 1983-02-22

Family

ID=14859563

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53123398A Expired JPS589626B2 (en) 1978-10-06 1978-10-06 digital signal receiver

Country Status (1)

Country Link
JP (1) JPS589626B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4510601A (en) * 1980-06-25 1985-04-09 Compagnie Industrielle Des Telecommunications Cit-Alcatel Digital frequency receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4510601A (en) * 1980-06-25 1985-04-09 Compagnie Industrielle Des Telecommunications Cit-Alcatel Digital frequency receiver

Also Published As

Publication number Publication date
JPS589626B2 (en) 1983-02-22

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