JPS5549047A - Fm receiver - Google Patents

Fm receiver

Info

Publication number
JPS5549047A
JPS5549047A JP12150778A JP12150778A JPS5549047A JP S5549047 A JPS5549047 A JP S5549047A JP 12150778 A JP12150778 A JP 12150778A JP 12150778 A JP12150778 A JP 12150778A JP S5549047 A JPS5549047 A JP S5549047A
Authority
JP
Japan
Prior art keywords
signal level
value
intermediate frequency
fixed value
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12150778A
Other languages
Japanese (ja)
Inventor
Yasuaki Kayano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12150778A priority Critical patent/JPS5549047A/en
Publication of JPS5549047A publication Critical patent/JPS5549047A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop

Landscapes

  • Noise Elimination (AREA)
  • Circuits Of Receivers In General (AREA)

Abstract

PURPOSE:To eliminate disturbance due to a multipulse by holding the input value of a voltage control oscillation circuit of a PLL circuit at the value right before a signal level of an intermediate frequency decreases below a fixed value. CONSTITUTION:An intermediate frequency is received by being inputted to PLL circuits 5, 6, and 7 and the signal level of the intermediate frequency is detected 3; when the detected signal level is below a fixed value, circuits 13 and 14 are provided which hold the input value of voltage control oscillator 7 of PLL circuits at a value right before the signal level decreases below the fixed value. As a result, influence due to disturbance of a multipulse can be avoided.
JP12150778A 1978-10-04 1978-10-04 Fm receiver Pending JPS5549047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12150778A JPS5549047A (en) 1978-10-04 1978-10-04 Fm receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12150778A JPS5549047A (en) 1978-10-04 1978-10-04 Fm receiver

Publications (1)

Publication Number Publication Date
JPS5549047A true JPS5549047A (en) 1980-04-08

Family

ID=14812899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12150778A Pending JPS5549047A (en) 1978-10-04 1978-10-04 Fm receiver

Country Status (1)

Country Link
JP (1) JPS5549047A (en)

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