JPS5548898A - Composite latch circuit - Google Patents
Composite latch circuitInfo
- Publication number
- JPS5548898A JPS5548898A JP12283678A JP12283678A JPS5548898A JP S5548898 A JPS5548898 A JP S5548898A JP 12283678 A JP12283678 A JP 12283678A JP 12283678 A JP12283678 A JP 12283678A JP S5548898 A JPS5548898 A JP S5548898A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- scan
- output
- shift
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
PURPOSE:To enable scan-in and out with less number of input and output lines and to make easy the formation of back up data, by setting the operation modes of a plurality through the use of a plurality of latch circuits in the logical system such as computer. CONSTITUTION:The latch circuit Lm and the shift latch circuit Fm are provided. Further, the circuit provides the normal operation mode setting data to the circuit Lm and setting the output of the circuit Lm to the circuit Fm, shift latch hold mode setting data to circuit Lm and holding the value of circuit Fm, shift mode shifting the output of circuit Fm while holding the value of circuit Lm, and scan-in mode setting the output of circuit Fm to circuit Lm. The circuit like those are assembled to the logic system to constitute the shift register of a suitable bit length, allowing to scan in, scan out and back up the data with less number of input and output lines.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53122836A JPS6051729B2 (en) | 1978-10-05 | 1978-10-05 | composite latch circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53122836A JPS6051729B2 (en) | 1978-10-05 | 1978-10-05 | composite latch circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5548898A true JPS5548898A (en) | 1980-04-08 |
JPS6051729B2 JPS6051729B2 (en) | 1985-11-15 |
Family
ID=14845828
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53122836A Expired JPS6051729B2 (en) | 1978-10-05 | 1978-10-05 | composite latch circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6051729B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58121447A (en) * | 1982-01-13 | 1983-07-19 | Nec Corp | Logical integrated circuit |
JPS59119443A (en) * | 1982-12-27 | 1984-07-10 | Toshiba Corp | Logic circuit |
JPS60116046A (en) * | 1983-11-28 | 1985-06-22 | Toshiba Corp | Logical circuit device |
JPS60193199A (en) * | 1983-12-05 | 1985-10-01 | テキサス インスツルメンツ インコ−ポレイテツド | Level sensitive latch stage |
-
1978
- 1978-10-05 JP JP53122836A patent/JPS6051729B2/en not_active Expired
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58121447A (en) * | 1982-01-13 | 1983-07-19 | Nec Corp | Logical integrated circuit |
JPH033251B2 (en) * | 1982-01-13 | 1991-01-18 | Nippon Electric Co | |
JPS59119443A (en) * | 1982-12-27 | 1984-07-10 | Toshiba Corp | Logic circuit |
JPS60116046A (en) * | 1983-11-28 | 1985-06-22 | Toshiba Corp | Logical circuit device |
JPS60193199A (en) * | 1983-12-05 | 1985-10-01 | テキサス インスツルメンツ インコ−ポレイテツド | Level sensitive latch stage |
Also Published As
Publication number | Publication date |
---|---|
JPS6051729B2 (en) | 1985-11-15 |
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