JPS5548821A - Phase synchronous circuit - Google Patents

Phase synchronous circuit

Info

Publication number
JPS5548821A
JPS5548821A JP12229278A JP12229278A JPS5548821A JP S5548821 A JPS5548821 A JP S5548821A JP 12229278 A JP12229278 A JP 12229278A JP 12229278 A JP12229278 A JP 12229278A JP S5548821 A JPS5548821 A JP S5548821A
Authority
JP
Japan
Prior art keywords
information
immediately before
phase difference
correction pulse
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12229278A
Other languages
Japanese (ja)
Inventor
Toshiki Okubo
Michitaka Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12229278A priority Critical patent/JPS5548821A/en
Publication of JPS5548821A publication Critical patent/JPS5548821A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To make stable the period of synchronizing signal, by delivering correction pulse from the information "0" appeared immediately after the information "1" obtained from the magnetic recorder.
CONSTITUTION: The phase detector 1, LPF 2 and voltage controlled oscillator 3 constitute the phase locked loop. When the information of the input information IN is "0", the characteristics of the information "1" immediately before it shifted toward "0" is used. That is, the latch circuit 8 storing the phase difference between the synchronizing signal and the information is provided, this is compared with the content of the counter 9 storing the phase difference immediately before, if it is greater than the phase difference immediately before by a given value, it is detected that the information coming next is "0". This detected output produces the correction pulse from the counter 9. Thus, the synchronism can be stabilized since the correction pulse correctly produces at the period of information "0".
COPYRIGHT: (C)1980,JPO&Japio
JP12229278A 1978-10-04 1978-10-04 Phase synchronous circuit Pending JPS5548821A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12229278A JPS5548821A (en) 1978-10-04 1978-10-04 Phase synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12229278A JPS5548821A (en) 1978-10-04 1978-10-04 Phase synchronous circuit

Publications (1)

Publication Number Publication Date
JPS5548821A true JPS5548821A (en) 1980-04-08

Family

ID=14832336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12229278A Pending JPS5548821A (en) 1978-10-04 1978-10-04 Phase synchronous circuit

Country Status (1)

Country Link
JP (1) JPS5548821A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999052215A1 (en) * 1998-03-31 1999-10-14 Fujitsu General Limited Phase-locked loop

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999052215A1 (en) * 1998-03-31 1999-10-14 Fujitsu General Limited Phase-locked loop

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