JPS5544257A - Virtual signal insertion system - Google Patents

Virtual signal insertion system

Info

Publication number
JPS5544257A
JPS5544257A JP11724778A JP11724778A JPS5544257A JP S5544257 A JPS5544257 A JP S5544257A JP 11724778 A JP11724778 A JP 11724778A JP 11724778 A JP11724778 A JP 11724778A JP S5544257 A JPS5544257 A JP S5544257A
Authority
JP
Japan
Prior art keywords
signal
circuit
input signal
virtual
virtual signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11724778A
Other languages
Japanese (ja)
Other versions
JPS5821457B2 (en
Inventor
Kazuo Ogawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53117247A priority Critical patent/JPS5821457B2/en
Publication of JPS5544257A publication Critical patent/JPS5544257A/en
Publication of JPS5821457B2 publication Critical patent/JPS5821457B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0602—Systems characterised by the synchronising information used

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To avoid the interference to closed other signals, by sufficiently making small the spike component, through the transmission of the input signal when the input signal is present and of the virtual signal when it is absent. CONSTITUTION:The input signal detection circuit 2 detects the presence of the input signal to produce output, and the virtual signal generation circuit 4 produces the virtual signal having the repetitive period different from the scramble pattern. Further, the switch circuit 3 operated with the output of the circuit 2 is provided, and when the input signal is present, the input signal is transmitted and when it is absent, the virtual signal from the circuit 4 is delivered to scramble the virtual signal of the circuit 4 at the absence of signal. Accordingly, spike shaped component is sufficiently reduced by inserting virtual signal at the absence of input and the transmission energy is sufficiently propagated, allowing to avoid interference to other communication closed.
JP53117247A 1978-09-22 1978-09-22 Pseudo signal input method Expired JPS5821457B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53117247A JPS5821457B2 (en) 1978-09-22 1978-09-22 Pseudo signal input method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53117247A JPS5821457B2 (en) 1978-09-22 1978-09-22 Pseudo signal input method

Publications (2)

Publication Number Publication Date
JPS5544257A true JPS5544257A (en) 1980-03-28
JPS5821457B2 JPS5821457B2 (en) 1983-04-30

Family

ID=14707024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53117247A Expired JPS5821457B2 (en) 1978-09-22 1978-09-22 Pseudo signal input method

Country Status (1)

Country Link
JP (1) JPS5821457B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214653A (en) * 1984-04-10 1985-10-26 Nec Corp Signal processor
JPH0411424A (en) * 1990-04-27 1992-01-16 Nec Corp Reset type scramble code transmission system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214653A (en) * 1984-04-10 1985-10-26 Nec Corp Signal processor
JPH0411424A (en) * 1990-04-27 1992-01-16 Nec Corp Reset type scramble code transmission system

Also Published As

Publication number Publication date
JPS5821457B2 (en) 1983-04-30

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