JPS5543194B2 - - Google Patents
Info
- Publication number
- JPS5543194B2 JPS5543194B2 JP13888475A JP13888475A JPS5543194B2 JP S5543194 B2 JPS5543194 B2 JP S5543194B2 JP 13888475 A JP13888475 A JP 13888475A JP 13888475 A JP13888475 A JP 13888475A JP S5543194 B2 JPS5543194 B2 JP S5543194B2
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50138884A JPS5263041A (en) | 1975-11-19 | 1975-11-19 | Buffer memory invalidation control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50138884A JPS5263041A (en) | 1975-11-19 | 1975-11-19 | Buffer memory invalidation control system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5263041A JPS5263041A (en) | 1977-05-25 |
JPS5543194B2 true JPS5543194B2 (no) | 1980-11-05 |
Family
ID=15232356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50138884A Granted JPS5263041A (en) | 1975-11-19 | 1975-11-19 | Buffer memory invalidation control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5263041A (no) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4345309A (en) * | 1980-01-28 | 1982-08-17 | Digital Equipment Corporation | Relating to cached multiprocessor system with pipeline timing |
JPH02110646A (ja) * | 1988-10-20 | 1990-04-23 | Hitachi Ltd | メモリの先行読出し装置 |
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1975
- 1975-11-19 JP JP50138884A patent/JPS5263041A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5263041A (en) | 1977-05-25 |