JPS5542489A - Multiplex information receiver - Google Patents

Abstract

PURPOSE: To eliminate the need for a buffer memory by writing a one-line picture signal transmitted at a period of two fields at the memory position of the final line of a memory at a period of two fields.

CONSTITUTION: Synchronizing with an information signal sent, rewriting clock generating circuit 14 generates a rewriting clocks at a rate of (n) bits per H. Those clocks are applied to memory 8 to write an picture signal, inputted through AND gate 20, into memory 8; the new left half of the picture signal is written to the (n)- bit part at the end part of memory 8 and the right half is given no signal. On the other hand, 2nN-n bits (N; the number of horizontal scanning lines of character information for one line) of a display clock generated by display clock generating circuit 15 are applied to memory 8 and the information picture of the left half is displayed on cathode-ray tube 10. At the next two equal fields, the (n)-bit rewriting clock is applied similarly to memory 8, where the picture information of the right half is written, and the display clock of 2nN bits is applied to memory 8 to display it on cathode-ray tube 10.

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