JPS5534568A - Present-office modification system - Google Patents

Present-office modification system

Info

Publication number
JPS5534568A
JPS5534568A JP10756178A JP10756178A JPS5534568A JP S5534568 A JPS5534568 A JP S5534568A JP 10756178 A JP10756178 A JP 10756178A JP 10756178 A JP10756178 A JP 10756178A JP S5534568 A JPS5534568 A JP S5534568A
Authority
JP
Japan
Prior art keywords
contents
memory
mcp
modified
line mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10756178A
Other languages
Japanese (ja)
Other versions
JPS5722510B2 (en
Inventor
Shiro Manabe
Shigeo Morita
Takeshi Kawasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP10756178A priority Critical patent/JPS5534568A/en
Publication of JPS5534568A publication Critical patent/JPS5534568A/en
Publication of JPS5722510B2 publication Critical patent/JPS5722510B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multi Processors (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE:To shorten a service interruption period of an electronic switchboard of a multiprocessor system, by modifying the memory contents of each memory in sequence when modifying office data recorded on each memory. CONSTITUTION:Under the control of main central processor MCP (CPN+1 and CPN+2, for example, serve as MCP), the contents of local memory IM corresponding to peripheral controllers NP corresponding to channel sub units SU are modified in sequence and the contents of IM of NPn+1 as ST-by NP are also updated lastly. The contents of common memory CM are modified from stand-by one, if equipped, and it is carried in an off-line mode when not. To modify the contents of IM corresponding to central processor CP, MCP puts corresponding CP in the off-line mode to update the contents of each IM and CP is put in the on-line mode while the right of MCP is given to other CP, so that unmodified memory contents will be modified under the control of new MCP.
JP10756178A 1978-09-04 1978-09-04 Present-office modification system Granted JPS5534568A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10756178A JPS5534568A (en) 1978-09-04 1978-09-04 Present-office modification system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10756178A JPS5534568A (en) 1978-09-04 1978-09-04 Present-office modification system

Publications (2)

Publication Number Publication Date
JPS5534568A true JPS5534568A (en) 1980-03-11
JPS5722510B2 JPS5722510B2 (en) 1982-05-13

Family

ID=14462286

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10756178A Granted JPS5534568A (en) 1978-09-04 1978-09-04 Present-office modification system

Country Status (1)

Country Link
JP (1) JPS5534568A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60106291A (en) * 1983-11-15 1985-06-11 Nec Corp Loading system of control program
JPS63107391A (en) * 1986-10-24 1988-05-12 Nec Corp Trunk data management system for distributed exchange
JPS63108894A (en) * 1986-10-24 1988-05-13 Nec Corp Station data managing system for distributed exchange
US11037710B2 (en) 2018-07-18 2021-06-15 Avx Corporation Varistor passivation layer and method of making the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6271193U (en) * 1985-10-22 1987-05-07

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60106291A (en) * 1983-11-15 1985-06-11 Nec Corp Loading system of control program
JPS63107391A (en) * 1986-10-24 1988-05-12 Nec Corp Trunk data management system for distributed exchange
JPS63108894A (en) * 1986-10-24 1988-05-13 Nec Corp Station data managing system for distributed exchange
US11037710B2 (en) 2018-07-18 2021-06-15 Avx Corporation Varistor passivation layer and method of making the same

Also Published As

Publication number Publication date
JPS5722510B2 (en) 1982-05-13

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