JPS553093A - Integrated circuit for development of computer - Google Patents
Integrated circuit for development of computerInfo
- Publication number
- JPS553093A JPS553093A JP7684278A JP7684278A JPS553093A JP S553093 A JPS553093 A JP S553093A JP 7684278 A JP7684278 A JP 7684278A JP 7684278 A JP7684278 A JP 7684278A JP S553093 A JPS553093 A JP S553093A
- Authority
- JP
- Japan
- Prior art keywords
- function
- gates
- input
- chip
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
PURPOSE: To insure the normal operation when the program is executed with only the order function featuring the lower-rank function by providing the selection circuit to select the orders according to each function in addition to part of each function in case each function of the microcomputer or the multiple chip is formed.
CONSTITUTION: Instruction decoder ID includes decoder blocks DA, DB, DC and DD each, and test terminal T to test the ever-chip plus signal line IP to be used as the signal line which supplies input to the prescribed register, buffer and others within the ever-chip through input boats IA, IB and IC each. Then input terminals of AND gates GA, GB and GC are connected to those input boats; and terminal T is connected to the other terminal respectively. Furthermore, the output of gate GA is connected to FF FA, the output of gates GB and GC are connected to FF FB and FC via OR gates OB and OC, and system reset signal R is connected to FF FAW FC each.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7684278A JPS553093A (en) | 1978-06-23 | 1978-06-23 | Integrated circuit for development of computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7684278A JPS553093A (en) | 1978-06-23 | 1978-06-23 | Integrated circuit for development of computer |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS553093A true JPS553093A (en) | 1980-01-10 |
JPS6131897B2 JPS6131897B2 (en) | 1986-07-23 |
Family
ID=13616912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7684278A Granted JPS553093A (en) | 1978-06-23 | 1978-06-23 | Integrated circuit for development of computer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS553093A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5835647A (en) * | 1981-08-27 | 1983-03-02 | Nec Corp | Appreciating device for microcomputer |
JPH04315231A (en) * | 1991-04-15 | 1992-11-06 | Sanyo Electric Co Ltd | Microcompuer for evaluation |
-
1978
- 1978-06-23 JP JP7684278A patent/JPS553093A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5835647A (en) * | 1981-08-27 | 1983-03-02 | Nec Corp | Appreciating device for microcomputer |
JPH0147811B2 (en) * | 1981-08-27 | 1989-10-17 | Nippon Electric Co | |
JPH04315231A (en) * | 1991-04-15 | 1992-11-06 | Sanyo Electric Co Ltd | Microcompuer for evaluation |
Also Published As
Publication number | Publication date |
---|---|
JPS6131897B2 (en) | 1986-07-23 |
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