JPS5528655A - Frequency discrimination circuit - Google Patents

Frequency discrimination circuit

Info

Publication number
JPS5528655A
JPS5528655A JP10219178A JP10219178A JPS5528655A JP S5528655 A JPS5528655 A JP S5528655A JP 10219178 A JP10219178 A JP 10219178A JP 10219178 A JP10219178 A JP 10219178A JP S5528655 A JPS5528655 A JP S5528655A
Authority
JP
Japan
Prior art keywords
signal
circuits
tuning
negative
half wave
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10219178A
Other languages
Japanese (ja)
Inventor
Isao Nakazawa
Takao Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10219178A priority Critical patent/JPS5528655A/en
Publication of JPS5528655A publication Critical patent/JPS5528655A/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE: To obtain the output signal of high performance, by using the negative feedback in place of the diode used for the level detection circuit and preventing the distortion of the demodulation signal by the level detection circuit.
CONSTITUTION: The frequency modulation signal inputted to the input terminal 1 is branched into two with the load tuning circuit 3, and after respective modulation signals are amplified at the amplifying transistors 4 and 5, they are fed to the tuning circuits 6 and 7. To the carrier frequency from the circuits 6 and 7, the tuning frequency symmetrical up and down is fed to the half wave linear rectifying circuits 21 and 31. The rectifying circuits 21 and 31 are provided with the doides 25 and 35 which half-wave-rectify the input signal and negative-feed-back it to the amplifiers 24 and 34, and with the diodes 26 and 36 which clamp the half wave of the input signal, and the high frequeny amplifying circuits 24 and 34. The operation at the rectifying circuits 21 and 31 can be detected at the linear part to the negative half wave of the input signal, and the detected signal is synthesized at the load resistors 10 and 11, to output a signal less in the distortion at the output terminal 12.
COPYRIGHT: (C)1980,JPO&Japio
JP10219178A 1978-08-22 1978-08-22 Frequency discrimination circuit Pending JPS5528655A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10219178A JPS5528655A (en) 1978-08-22 1978-08-22 Frequency discrimination circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10219178A JPS5528655A (en) 1978-08-22 1978-08-22 Frequency discrimination circuit

Publications (1)

Publication Number Publication Date
JPS5528655A true JPS5528655A (en) 1980-02-29

Family

ID=14320765

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10219178A Pending JPS5528655A (en) 1978-08-22 1978-08-22 Frequency discrimination circuit

Country Status (1)

Country Link
JP (1) JPS5528655A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52116832A (en) * 1976-03-26 1977-09-30 Hewlett Packard Yokogawa Rectifying circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52116832A (en) * 1976-03-26 1977-09-30 Hewlett Packard Yokogawa Rectifying circuit

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