JPS5525291A - Serial data transmission device - Google Patents

Serial data transmission device

Info

Publication number
JPS5525291A
JPS5525291A JP9883578A JP9883578A JPS5525291A JP S5525291 A JPS5525291 A JP S5525291A JP 9883578 A JP9883578 A JP 9883578A JP 9883578 A JP9883578 A JP 9883578A JP S5525291 A JPS5525291 A JP S5525291A
Authority
JP
Japan
Prior art keywords
data
circuit
transmission
parity
length
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9883578A
Other languages
Japanese (ja)
Inventor
Hiroshi Mitsui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP9883578A priority Critical patent/JPS5525291A/en
Publication of JPS5525291A publication Critical patent/JPS5525291A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00Arrangements for detecting or preventing errors in the information received
    • H04L1/004Arrangements for detecting or preventing errors in the information received by using forward error control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To facilitate the setting of the data length and to secure handling of the variable length data by adding the contents of the parity memory part to the end of the transmission data as the parity via the parity bit transmission signal given from the counter circuit for transmission of the data. CONSTITUTION:Parallel-serial conversion circuit 1 converts the parallel data into the serial data. Counter circuit 13 sets the bit length of the transmission data, the clock pulse is generated from clock circuit 4 in relation to circuit 3, and the parity information is memorized in parity memory part 5 to be held. Then the parallel data is supplied to circuit 1, and the serial transmission data is transmitted from circuit 1 synchronization with the clock pulse sent from circuit 4. At the same time, the data is led to part 5 to produce the parity bit. Then the contents of part 5 then is added to the end of the transmission data as the parity bit for transmission via the parity bit transmission signal sent from circuit 3. As a result, the setting is facilitated for the data length to ensure handling of the variable length data.
JP9883578A 1978-08-11 1978-08-11 Serial data transmission device Pending JPS5525291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9883578A JPS5525291A (en) 1978-08-11 1978-08-11 Serial data transmission device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9883578A JPS5525291A (en) 1978-08-11 1978-08-11 Serial data transmission device

Publications (1)

Publication Number Publication Date
JPS5525291A true JPS5525291A (en) 1980-02-22

Family

ID=14230320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9883578A Pending JPS5525291A (en) 1978-08-11 1978-08-11 Serial data transmission device

Country Status (1)

Country Link
JP (1) JPS5525291A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936454A (en) * 1982-05-11 1984-02-28 タンダム・コンピユ−タ−ズ・インコ−ポレ−テツド Scrambler encoder integrated and using quasi-random sequence generator
JPS6156529A (en) * 1984-07-27 1986-03-22 Fujitsu Ltd Adaptive parity check system
JPS61103298A (en) * 1984-10-26 1986-05-21 富士ゼロックス株式会社 Controller for copying machine
JPS62166632A (en) * 1986-01-20 1987-07-23 Matsushita Electric Ind Co Ltd Data communication system
JPH0318127A (en) * 1989-06-14 1991-01-25 Fujitsu Ltd Parity arithmetic circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5370705A (en) * 1976-12-07 1978-06-23 Fujitsu Ltd Parity generator circuit for transmission data

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5370705A (en) * 1976-12-07 1978-06-23 Fujitsu Ltd Parity generator circuit for transmission data

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5936454A (en) * 1982-05-11 1984-02-28 タンダム・コンピユ−タ−ズ・インコ−ポレ−テツド Scrambler encoder integrated and using quasi-random sequence generator
JPS6156529A (en) * 1984-07-27 1986-03-22 Fujitsu Ltd Adaptive parity check system
JPS61103298A (en) * 1984-10-26 1986-05-21 富士ゼロックス株式会社 Controller for copying machine
JPS62166632A (en) * 1986-01-20 1987-07-23 Matsushita Electric Ind Co Ltd Data communication system
JPH0318127A (en) * 1989-06-14 1991-01-25 Fujitsu Ltd Parity arithmetic circuit

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