JPS5525240A - Synchronous data transmission system - Google Patents

Synchronous data transmission system

Info

Publication number
JPS5525240A
JPS5525240A JP9787778A JP9787778A JPS5525240A JP S5525240 A JPS5525240 A JP S5525240A JP 9787778 A JP9787778 A JP 9787778A JP 9787778 A JP9787778 A JP 9787778A JP S5525240 A JPS5525240 A JP S5525240A
Authority
JP
Japan
Prior art keywords
signal
synchronous
circuit
time duration
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9787778A
Other languages
Japanese (ja)
Inventor
Makoto Kawai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP9787778A priority Critical patent/JPS5525240A/en
Publication of JPS5525240A publication Critical patent/JPS5525240A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/08—Speed or phase control by synchronisation signals the synchronisation signals recurring cyclically

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To secure the synchronous data transmission in a simple way via a single circuit by forming the synchronous signal part with the asymmetric clock signal. CONSTITUTION:Synchronous signal ST is supplied to NAND gate 1 along with clock signal CP to obtain output (a). Signal (a) is piled on the data signal to obtain signal (b). Signal (b) is transmitted via single circuit l. At the reception side noise (n) mixed in from input signal (c) is eliminated, and output (d) is supplied to data signal detection circuit 8 and synchronous signal detection circuit 7. Circuit 8 compensates the break part of signal (d) via the one-shot multi which is a little longer than time duration (t). Circuit 7 possesses the one-shot multi featuring time duration T and compensates the break part of signal (e) supplied via one-shot multi-vibrator 6 of time duration 1.5T to obtain synchronous signal RT.
JP9787778A 1978-08-10 1978-08-10 Synchronous data transmission system Pending JPS5525240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9787778A JPS5525240A (en) 1978-08-10 1978-08-10 Synchronous data transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9787778A JPS5525240A (en) 1978-08-10 1978-08-10 Synchronous data transmission system

Publications (1)

Publication Number Publication Date
JPS5525240A true JPS5525240A (en) 1980-02-22

Family

ID=14203969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9787778A Pending JPS5525240A (en) 1978-08-10 1978-08-10 Synchronous data transmission system

Country Status (1)

Country Link
JP (1) JPS5525240A (en)

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