JPS5525109A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS5525109A
JPS5525109A JP9696578A JP9696578A JPS5525109A JP S5525109 A JPS5525109 A JP S5525109A JP 9696578 A JP9696578 A JP 9696578A JP 9696578 A JP9696578 A JP 9696578A JP S5525109 A JPS5525109 A JP S5525109A
Authority
JP
Japan
Prior art keywords
memory element
element group
signal
logic
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9696578A
Other languages
Japanese (ja)
Inventor
Moriyuki Takamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9696578A priority Critical patent/JPS5525109A/en
Publication of JPS5525109A publication Critical patent/JPS5525109A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Logic Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To make tests of a memory element easily by making it possible to input and output direct a signal between the memory element and the outside of a printed circuit board where the memory element and logic element are mounted to form a logic circuit.
CONSTITUTION: Either one of an external inout signal from terminal 5 and a signal from logic element group 2 is selected by multiplexer 7 and inputted to memory element group 3. Corresponding to it, either address from terminal 19 or logic element group 16 is selected by multiplexer 18 and supplied to memory element group 3. Read-out data from memory element group 3 are applied to logic element group 33 and also led to terminal 35 via drive 34. The signal selection by multiplexers is carried out by control signals.
COPYRIGHT: (C)1980,JPO&Japio
JP9696578A 1978-08-09 1978-08-09 Logic circuit Pending JPS5525109A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9696578A JPS5525109A (en) 1978-08-09 1978-08-09 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9696578A JPS5525109A (en) 1978-08-09 1978-08-09 Logic circuit

Publications (1)

Publication Number Publication Date
JPS5525109A true JPS5525109A (en) 1980-02-22

Family

ID=14178941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9696578A Pending JPS5525109A (en) 1978-08-09 1978-08-09 Logic circuit

Country Status (1)

Country Link
JP (1) JPS5525109A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60103169U (en) * 1983-12-19 1985-07-13 櫻紙管工業株式会社 Structure of paper tube mouthpiece
JPS63123561U (en) * 1987-01-30 1988-08-11

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5184530A (en) * 1974-12-20 1976-07-23 Ibm Memori areino chokusetsutekitesutookanonishita lsi handotaidebaisu

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5184530A (en) * 1974-12-20 1976-07-23 Ibm Memori areino chokusetsutekitesutookanonishita lsi handotaidebaisu

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60103169U (en) * 1983-12-19 1985-07-13 櫻紙管工業株式会社 Structure of paper tube mouthpiece
JPS63123561U (en) * 1987-01-30 1988-08-11

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