JPS5524420A - Insulated gate type filed effect transistor - Google Patents

Insulated gate type filed effect transistor

Info

Publication number
JPS5524420A
JPS5524420A JP9667078A JP9667078A JPS5524420A JP S5524420 A JPS5524420 A JP S5524420A JP 9667078 A JP9667078 A JP 9667078A JP 9667078 A JP9667078 A JP 9667078A JP S5524420 A JPS5524420 A JP S5524420A
Authority
JP
Japan
Prior art keywords
film
gate electrode
gate
etched
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9667078A
Other languages
Japanese (ja)
Inventor
Kazumasa Onodera
Kyozo Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP9667078A priority Critical patent/JPS5524420A/en
Publication of JPS5524420A publication Critical patent/JPS5524420A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain such device as is minute and free from junction leak current by forming a source and a drain with gate metal capable of resisting high temperatures and oxidizing the periphery, which are changeable in thickness in two steps through self-matching.
CONSTITUTION: A W-film 24 is formed on a gate oxidized film 23. Next, a photoresist 26 is provided and a mask 27 is given which is stepped by selective exposure. The resist 26 is etched to leave a resist 33 on a W-film 30 and after the W-film 30 is etched with the mask 33, a gate electrode 36 covered with an insulating film 35 is formed through anodic oxidation. Next, a stepped source and drain are provided by ion injection, and an elimination of defective crystals and a positioning of the gate electrode end and the shallow junction end are carried out through heat treatment. Next, Al wiring layer 39 is formed, which is not short-circuited with the gate electrode for its being insulated. Finally Si3N4 40 is grown to completion at low temperatures. According to this constitution, even short channels are not punched through and a junction leak does not result from short circuit between the external wiring and the substrate, thus securing such memory as is miniaturized and lasts long.
COPYRIGHT: (C)1980,JPO&Japio
JP9667078A 1978-08-10 1978-08-10 Insulated gate type filed effect transistor Pending JPS5524420A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9667078A JPS5524420A (en) 1978-08-10 1978-08-10 Insulated gate type filed effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9667078A JPS5524420A (en) 1978-08-10 1978-08-10 Insulated gate type filed effect transistor

Publications (1)

Publication Number Publication Date
JPS5524420A true JPS5524420A (en) 1980-02-21

Family

ID=14171233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9667078A Pending JPS5524420A (en) 1978-08-10 1978-08-10 Insulated gate type filed effect transistor

Country Status (1)

Country Link
JP (1) JPS5524420A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0513590A2 (en) * 1991-05-08 1992-11-19 Seiko Epson Corporation Thin-film transistor and method for manufacturing it
JPH0590292A (en) * 1991-09-30 1993-04-09 Semiconductor Energy Lab Co Ltd Semiconductor integrated circuit and manufacture thereof
US5770486A (en) * 1993-03-22 1998-06-23 Semiconductor Energy Lab Method of forming a transistor with an LDD structure
US6323528B1 (en) 1991-03-06 2001-11-27 Semiconductor Energy Laboratory Co,. Ltd. Semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4827506A (en) * 1971-08-19 1973-04-11
JPS5347781A (en) * 1976-10-13 1978-04-28 Hitachi Ltd Production of silicon gate semiconductor device
JPS5382268A (en) * 1976-12-28 1978-07-20 Toshiba Corp Production of mask
JPS5389374A (en) * 1977-01-18 1978-08-05 Toshiba Corp Production of semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4827506A (en) * 1971-08-19 1973-04-11
JPS5347781A (en) * 1976-10-13 1978-04-28 Hitachi Ltd Production of silicon gate semiconductor device
JPS5382268A (en) * 1976-12-28 1978-07-20 Toshiba Corp Production of mask
JPS5389374A (en) * 1977-01-18 1978-08-05 Toshiba Corp Production of semiconductor device

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6323528B1 (en) 1991-03-06 2001-11-27 Semiconductor Energy Laboratory Co,. Ltd. Semiconductor device
US6822261B2 (en) 1991-03-06 2004-11-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
EP0513590A2 (en) * 1991-05-08 1992-11-19 Seiko Epson Corporation Thin-film transistor and method for manufacturing it
US5561075A (en) * 1991-05-08 1996-10-01 Seiko Epson Corporation Method of manufacturing an active matrix panel
US5583366A (en) * 1991-05-08 1996-12-10 Seiko Epson Corporation Active matrix panel
US5814539A (en) * 1991-05-08 1998-09-29 Seiko Epson Corporation Method of manufacturing an active matrix panel
US6136625A (en) * 1991-05-08 2000-10-24 Seiko Epson Corporation Method of manufacturing an active matrix panel
JPH0590292A (en) * 1991-09-30 1993-04-09 Semiconductor Energy Lab Co Ltd Semiconductor integrated circuit and manufacture thereof
US5770486A (en) * 1993-03-22 1998-06-23 Semiconductor Energy Lab Method of forming a transistor with an LDD structure

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