JPS5523698A - Reception unit - Google Patents

Reception unit

Info

Publication number
JPS5523698A
JPS5523698A JP10008979A JP10008979A JPS5523698A JP S5523698 A JPS5523698 A JP S5523698A JP 10008979 A JP10008979 A JP 10008979A JP 10008979 A JP10008979 A JP 10008979A JP S5523698 A JPS5523698 A JP S5523698A
Authority
JP
Japan
Prior art keywords
channel selection
output
desired broadcast
generation circuit
pulse generation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10008979A
Other languages
Japanese (ja)
Other versions
JPS5525547B2 (en
Inventor
Osamu Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP10008979A priority Critical patent/JPS5523698A/en
Publication of JPS5523698A publication Critical patent/JPS5523698A/en
Publication of JPS5525547B2 publication Critical patent/JPS5525547B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J5/00—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner
    • H03J5/02—Discontinuous tuning; Selecting predetermined frequencies; Selecting frequency bands with or without continuous tuning in one or more of the bands, e.g. push-button tuning, turret tuner with variable tuning element having a number of predetermined settings and adjustable to a desired one of these settings
    • H03J5/0245—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form
    • H03J5/0272—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer
    • H03J5/0281—Discontinuous tuning using an electrical variable impedance element, e.g. a voltage variable reactive diode, in which no corresponding analogue value either exists or is preset, i.e. the tuning information is only available in a digital form the digital values being used to preset a counter or a frequency divider in a phase locked loop, e.g. frequency synthesizer the digital values being held in an auxiliary non erasable memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Superheterodyne Receivers (AREA)
  • Circuits Of Receivers In General (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To make easy the channel selection operation for desired broadcast stations, by changing the count value of the binary channel selection counter through the control of the channel selection pulse generation circuit to display and store all the desired broadcast station receptionable. CONSTITUTION:The channel selection binary counter 14 counts the output of the channel selection pulse generation circuit, the output controls the frequency dividing ratio of the 1/N frequency divider 9, and the output demultiplying the output of the local oscillator with the divider 9 and that of the reference oscillator 11 are compared for the phase 10. The output of the binary-decimal decoder 20 is fed to the matrix decoder 24, which outputs two sets of row address signal and column address signal, performs matrix display 47, and gives the row and column address signals of other sets to the matrix memories 59N and 59P. Further, by controlling the channel selection pulse generation circuit and changing the count value of the counter 14, all the desired broadcast stations receptionable are displayed 47 and they are written in the memories 59N and 59P. Thus, the channel selection for desired broadcast stations can be made easily.
JP10008979A 1979-08-06 1979-08-06 Reception unit Granted JPS5523698A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10008979A JPS5523698A (en) 1979-08-06 1979-08-06 Reception unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10008979A JPS5523698A (en) 1979-08-06 1979-08-06 Reception unit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9605671A Division JPS555729B2 (en) 1971-11-29 1971-11-29

Publications (2)

Publication Number Publication Date
JPS5523698A true JPS5523698A (en) 1980-02-20
JPS5525547B2 JPS5525547B2 (en) 1980-07-07

Family

ID=14264687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10008979A Granted JPS5523698A (en) 1979-08-06 1979-08-06 Reception unit

Country Status (1)

Country Link
JP (1) JPS5523698A (en)

Also Published As

Publication number Publication date
JPS5525547B2 (en) 1980-07-07

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