JPS5522830A - Unit cell for logic lsi chip - Google Patents
Unit cell for logic lsi chipInfo
- Publication number
- JPS5522830A JPS5522830A JP9522778A JP9522778A JPS5522830A JP S5522830 A JPS5522830 A JP S5522830A JP 9522778 A JP9522778 A JP 9522778A JP 9522778 A JP9522778 A JP 9522778A JP S5522830 A JPS5522830 A JP S5522830A
- Authority
- JP
- Japan
- Prior art keywords
- wirings
- cells
- right angles
- input
- cross
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012938 design process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11801—Masterslice integrated circuits using bipolar technology
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To effect the reduction in chip size by arranging plural logic elements to cross at right angles with the wirings between cells extending in straight-lines, providing the input and output wirings also to cross at right angles with the wirings between cells and then optionally connecting the input and output wirings with the wirings between cells. CONSTITUTION:Wirings 12-16 between cells are formed in parallel and straight- lines, at right angles with which transistors 1-7 are arranged. Resistance elements 8-11 are also arranged in the same manner, and the wirings 12-16 between cells are connected to the corresponding elements via throughholes. Next, wirings 17-20 serving as input and output terminals are arranged to cross at right angles with the wirings 12-16 and then wirings 17-20 and 12-16 are connected to each other at crosspoints therebetween. In other words, wirings between cells are provided at either of points shown by 21-23 optionally and connected to a wiring 19. This leads to the reduction in size, particularly in lateral direction, and the automization in the mask design process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9522778A JPS5522830A (en) | 1978-08-04 | 1978-08-04 | Unit cell for logic lsi chip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9522778A JPS5522830A (en) | 1978-08-04 | 1978-08-04 | Unit cell for logic lsi chip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5522830A true JPS5522830A (en) | 1980-02-18 |
Family
ID=14131862
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9522778A Pending JPS5522830A (en) | 1978-08-04 | 1978-08-04 | Unit cell for logic lsi chip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5522830A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63176866U (en) * | 1987-02-21 | 1988-11-16 | ||
US5468977A (en) * | 1990-10-23 | 1995-11-21 | Mitsubishi Denki Kabushiki Kaisha | Standard cells interconnection structure including a modified standard cell |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS522386A (en) * | 1975-06-23 | 1977-01-10 | Ibm | Semiconductor chip |
-
1978
- 1978-08-04 JP JP9522778A patent/JPS5522830A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS522386A (en) * | 1975-06-23 | 1977-01-10 | Ibm | Semiconductor chip |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63176866U (en) * | 1987-02-21 | 1988-11-16 | ||
US5468977A (en) * | 1990-10-23 | 1995-11-21 | Mitsubishi Denki Kabushiki Kaisha | Standard cells interconnection structure including a modified standard cell |
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