JPS5518124A - Digital-analog coupling circuit - Google Patents

Digital-analog coupling circuit

Info

Publication number
JPS5518124A
JPS5518124A JP9061178A JP9061178A JPS5518124A JP S5518124 A JPS5518124 A JP S5518124A JP 9061178 A JP9061178 A JP 9061178A JP 9061178 A JP9061178 A JP 9061178A JP S5518124 A JPS5518124 A JP S5518124A
Authority
JP
Japan
Prior art keywords
circuit
digital
supplied
output
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9061178A
Other languages
Japanese (ja)
Inventor
Hiroshi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9061178A priority Critical patent/JPS5518124A/en
Publication of JPS5518124A publication Critical patent/JPS5518124A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H03K19/018521—Interface arrangements of complementary type, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To secure an easy coupling between the digital and analog circuit without giving the evil effect to the operation of the alanog circuit and with facilitated monolithic formation by forming the output step of the digital circuit with the tristate burrer. CONSTITUTION:The output signals of digital circuit 1 are supplied to NAND circuit 2 which is gate-controlled by the control signal supplied via inverter circuit 4 as well as to NOR circuit 3 which is controlled by the control signal inverted again via inverter circuit 5. The output of circuit 2 and 3 are supplied to the tristate buffer composed of vertically connected complementary transistor (C-MOS) 6 and 7, and the output is supplied to analog circuit 8. Then both transistors 6 and 7 receive the OFF control by the control signal to cut off the signal transmission from circuit 1 to 8.
JP9061178A 1978-07-25 1978-07-25 Digital-analog coupling circuit Pending JPS5518124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9061178A JPS5518124A (en) 1978-07-25 1978-07-25 Digital-analog coupling circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9061178A JPS5518124A (en) 1978-07-25 1978-07-25 Digital-analog coupling circuit

Publications (1)

Publication Number Publication Date
JPS5518124A true JPS5518124A (en) 1980-02-08

Family

ID=14003267

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9061178A Pending JPS5518124A (en) 1978-07-25 1978-07-25 Digital-analog coupling circuit

Country Status (1)

Country Link
JP (1) JPS5518124A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103795395A (en) * 2014-01-20 2014-05-14 海能达通信股份有限公司 Analog circuit device for anti-shake time slot synchronization

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103795395A (en) * 2014-01-20 2014-05-14 海能达通信股份有限公司 Analog circuit device for anti-shake time slot synchronization
CN103795395B (en) * 2014-01-20 2016-05-04 海能达通信股份有限公司 A kind of mould electric installation for anti-shake slot synchronization

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