JPS55162628A - Wave shaping circuit - Google Patents
Wave shaping circuitInfo
- Publication number
- JPS55162628A JPS55162628A JP6984279A JP6984279A JPS55162628A JP S55162628 A JPS55162628 A JP S55162628A JP 6984279 A JP6984279 A JP 6984279A JP 6984279 A JP6984279 A JP 6984279A JP S55162628 A JPS55162628 A JP S55162628A
- Authority
- JP
- Japan
- Prior art keywords
- cmos inverter
- circuit
- wave shaping
- shaping circuit
- clocked
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/354—Astable circuits
- H03K3/3545—Stabilisation of output, e.g. using crystal
Landscapes
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To enable to make the stop voltage to a very low voltage, by making variable the mutual conductance of the inversion amplifying circuit, through the detection of wear of battery automatically. CONSTITUTION:A crystal oscillation circuit 7 is formed with a parallel connection of CMOS inverter 4, clocked CMOS inverter 9, resistor RF and crystal oscillator. The wave shaping circuit 8 is formed with a parallel connection of CMOS inverter 10, and clocked CMOS inverter 11 taking the signals A, B as clock inputs. Further, the internl circuit 5 consists of the frequency dividing circuit receiving the output of the wave shaping circuit 8. When the terminal voltage of the battery is lowered, the clocked CMOS inverter 11 is automtically in parallel connetion, the wave shaping is made with two sets of inverters 10 and 11, to increases the mutual conductance equivalently.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6984279A JPS55162628A (en) | 1979-06-06 | 1979-06-06 | Wave shaping circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6984279A JPS55162628A (en) | 1979-06-06 | 1979-06-06 | Wave shaping circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55162628A true JPS55162628A (en) | 1980-12-18 |
Family
ID=13414452
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6984279A Pending JPS55162628A (en) | 1979-06-06 | 1979-06-06 | Wave shaping circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55162628A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1993005466A1 (en) * | 1991-09-04 | 1993-03-18 | Seiko Epson Corporation | Oscillator |
WO2017129767A1 (en) * | 2016-01-29 | 2017-08-03 | Abb Schweiz Ag | Failure tolerant capacitor device |
-
1979
- 1979-06-06 JP JP6984279A patent/JPS55162628A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1993005466A1 (en) * | 1991-09-04 | 1993-03-18 | Seiko Epson Corporation | Oscillator |
WO2017129767A1 (en) * | 2016-01-29 | 2017-08-03 | Abb Schweiz Ag | Failure tolerant capacitor device |
CN108496086A (en) * | 2016-01-29 | 2018-09-04 | Abb瑞士股份有限公司 | Failure allows capacitor device |
CN108496086B (en) * | 2016-01-29 | 2019-07-05 | Abb瑞士股份有限公司 | Failure allows capacitor device |
US10386403B2 (en) | 2016-01-29 | 2019-08-20 | Abb Schweiz Ag | Failure tolerant capacitor device |
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