JPS55153391A - Method of forming circuit - Google Patents

Method of forming circuit

Info

Publication number
JPS55153391A
JPS55153391A JP5974879A JP5974879A JPS55153391A JP S55153391 A JPS55153391 A JP S55153391A JP 5974879 A JP5974879 A JP 5974879A JP 5974879 A JP5974879 A JP 5974879A JP S55153391 A JPS55153391 A JP S55153391A
Authority
JP
Japan
Prior art keywords
forming circuit
circuit
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5974879A
Other languages
Japanese (ja)
Inventor
Setsuo Suzuki
Yasuo Matsui
Jiyunko Takeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Bakelite Co Ltd
Original Assignee
Sumitomo Bakelite Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Bakelite Co Ltd filed Critical Sumitomo Bakelite Co Ltd
Priority to JP5974879A priority Critical patent/JPS55153391A/en
Publication of JPS55153391A publication Critical patent/JPS55153391A/en
Pending legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
JP5974879A 1979-05-17 1979-05-17 Method of forming circuit Pending JPS55153391A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5974879A JPS55153391A (en) 1979-05-17 1979-05-17 Method of forming circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5974879A JPS55153391A (en) 1979-05-17 1979-05-17 Method of forming circuit

Publications (1)

Publication Number Publication Date
JPS55153391A true JPS55153391A (en) 1980-11-29

Family

ID=13122159

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5974879A Pending JPS55153391A (en) 1979-05-17 1979-05-17 Method of forming circuit

Country Status (1)

Country Link
JP (1) JPS55153391A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052089A (en) * 1983-06-24 1985-03-23 アモコ・コ−ポレイション Printing circuit
JPS63142695A (en) * 1986-12-05 1988-06-15 新神戸電機株式会社 Manufacture of printed circuit board with resistance circuit
JP2007184631A (en) * 2001-06-05 2007-07-19 Dainippon Printing Co Ltd Manufacturing method of wiring board equipped with passive element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4963999A (en) * 1972-10-27 1974-06-20
JPS5250572A (en) * 1975-10-20 1977-04-22 Fujitsu Ltd Method of producing bothhside printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4963999A (en) * 1972-10-27 1974-06-20
JPS5250572A (en) * 1975-10-20 1977-04-22 Fujitsu Ltd Method of producing bothhside printed circuit board

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052089A (en) * 1983-06-24 1985-03-23 アモコ・コ−ポレイション Printing circuit
JPH0370917B2 (en) * 1983-06-24 1991-11-11 Amoco Corp
JPS63142695A (en) * 1986-12-05 1988-06-15 新神戸電機株式会社 Manufacture of printed circuit board with resistance circuit
JP2007184631A (en) * 2001-06-05 2007-07-19 Dainippon Printing Co Ltd Manufacturing method of wiring board equipped with passive element
JP4515477B2 (en) * 2001-06-05 2010-07-28 大日本印刷株式会社 Method for manufacturing wiring board with passive element

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