JPS55122286A - Data processing system - Google Patents
Data processing systemInfo
- Publication number
- JPS55122286A JPS55122286A JP2797879A JP2797879A JPS55122286A JP S55122286 A JPS55122286 A JP S55122286A JP 2797879 A JP2797879 A JP 2797879A JP 2797879 A JP2797879 A JP 2797879A JP S55122286 A JPS55122286 A JP S55122286A
- Authority
- JP
- Japan
- Prior art keywords
- bits
- memory
- address
- csm
- capacity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To improve a hit rate by causing the address of a cash memory and the address to a map register to overlap each other.
CONSTITUTION: Map register MPR converts only upper 8 bits of precribed-bits, for example 19-bits CPU logical address CPA to generate a 13-bits actual address and applies this address to comparator CMP. Next, 11 bits of the rest of 19 bits are inputted to the upper address part of cash memory CSM. In this case, two bits out of 11 bits and lower bits of upper 8 bits are caused to overlap each other. Therefore, a 22=4-multiplied memory capacity is required because two bits of overlapping components are inputted extra to memory CSM. The semiconductor IC memory used for memory CSM can achieve very easily and cheaply four-times capacity increment due to rapid progress in production technique. As a result, since the capacity of memory CSM may be increased by a unit memory, the hit rate can be improved.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2797879A JPS55122286A (en) | 1979-03-10 | 1979-03-10 | Data processing system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2797879A JPS55122286A (en) | 1979-03-10 | 1979-03-10 | Data processing system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55122286A true JPS55122286A (en) | 1980-09-19 |
Family
ID=12235941
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2797879A Pending JPS55122286A (en) | 1979-03-10 | 1979-03-10 | Data processing system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55122286A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57100682A (en) * | 1980-12-15 | 1982-06-22 | Nec Corp | Address buffer memory system |
JPS58150186A (en) * | 1982-03-03 | 1983-09-06 | Nec Corp | System for controlling buffer memory |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52112240A (en) * | 1976-03-17 | 1977-09-20 | Fujitsu Ltd | Data processing unit |
JPS5415620A (en) * | 1977-07-06 | 1979-02-05 | Nec Corp | Buffer memory unit |
-
1979
- 1979-03-10 JP JP2797879A patent/JPS55122286A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52112240A (en) * | 1976-03-17 | 1977-09-20 | Fujitsu Ltd | Data processing unit |
JPS5415620A (en) * | 1977-07-06 | 1979-02-05 | Nec Corp | Buffer memory unit |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57100682A (en) * | 1980-12-15 | 1982-06-22 | Nec Corp | Address buffer memory system |
JPS58150186A (en) * | 1982-03-03 | 1983-09-06 | Nec Corp | System for controlling buffer memory |
JPS6213699B2 (en) * | 1982-03-03 | 1987-03-28 | Nippon Electric Co |
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