JPS548871A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS548871A
JPS548871A JP7472977A JP7472977A JPS548871A JP S548871 A JPS548871 A JP S548871A JP 7472977 A JP7472977 A JP 7472977A JP 7472977 A JP7472977 A JP 7472977A JP S548871 A JPS548871 A JP S548871A
Authority
JP
Japan
Prior art keywords
circuit
printed
configuration
conductors
plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7472977A
Other languages
Japanese (ja)
Inventor
Kazuo Kawasumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suwa Seikosha KK
Original Assignee
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suwa Seikosha KK filed Critical Suwa Seikosha KK
Priority to JP7472977A priority Critical patent/JPS548871A/en
Priority to CH688678A priority patent/CH638947GA3/en
Publication of JPS548871A publication Critical patent/JPS548871A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • GPHYSICS
    • G04HOROLOGY
    • G04GELECTRONIC TIME-PIECES
    • G04G17/00Structural details; Housings
    • G04G17/02Component assemblies
    • G04G17/04Mounting of electronic components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electric Clocks (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
  • Electromechanical Clocks (AREA)

Abstract

A circuit for an electronic timepiece, especially for an electronic wristwatch, comprises a plate or printed-circuit sheet (1) carrying a configuration of conductors (1a) whose various points receive electrical connections of an integrated circuit (3). An aperture (1b) is made in the plate or printed-circuit sheet, and a metal plate (11) is affixed, by adhesion, to the back of the printed circuit (1). The integrated circuit board (3) is arranged in this aperture and it is connected by fine, very short conductors (5) to the configuration of conductors (1a). A plastic coating (6) is arranged over the printed circuit board (3) and over the latter's connections with the configuration and to the conductor. This circuit allows very thin construction and easy manufacture of the electronic watch. <IMAGE>
JP7472977A 1977-06-23 1977-06-23 Semiconductor device Pending JPS548871A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7472977A JPS548871A (en) 1977-06-23 1977-06-23 Semiconductor device
CH688678A CH638947GA3 (en) 1977-06-23 1978-06-23 Circuit for electronic timepiece, especially for an electronic wristwatch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7472977A JPS548871A (en) 1977-06-23 1977-06-23 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS548871A true JPS548871A (en) 1979-01-23

Family

ID=13555592

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7472977A Pending JPS548871A (en) 1977-06-23 1977-06-23 Semiconductor device

Country Status (2)

Country Link
JP (1) JPS548871A (en)
CH (1) CH638947GA3 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608440A (en) * 1983-06-29 1985-01-17 Toyota Motor Corp Control of idling speed control system
JP2009030842A (en) * 2007-07-25 2009-02-12 Sharp Corp Humidifier and filter
JP2010025360A (en) * 2008-07-15 2010-02-04 Daikin Ind Ltd Humidifying device
US8382073B2 (en) 2007-07-18 2013-02-26 Sharp Kabushiki Kaisha Humidifier, filter unit and rotation drive structure
USRE45146E1 (en) 2002-05-30 2014-09-23 Taiyo Yuden Co., Ltd Composite multi-layer substrate and module using the substrate
WO2017169421A1 (en) * 2016-03-29 2017-10-05 ポリマテック・ジャパン株式会社 Flexible circuit board and method for manufacturing flexible circuit board

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE29714186U1 (en) * 1997-08-08 1998-12-10 Junghans Gmbh Geb Radio clockwork

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS608440A (en) * 1983-06-29 1985-01-17 Toyota Motor Corp Control of idling speed control system
USRE45146E1 (en) 2002-05-30 2014-09-23 Taiyo Yuden Co., Ltd Composite multi-layer substrate and module using the substrate
US8382073B2 (en) 2007-07-18 2013-02-26 Sharp Kabushiki Kaisha Humidifier, filter unit and rotation drive structure
JP2009030842A (en) * 2007-07-25 2009-02-12 Sharp Corp Humidifier and filter
JP2010025360A (en) * 2008-07-15 2010-02-04 Daikin Ind Ltd Humidifying device
WO2017169421A1 (en) * 2016-03-29 2017-10-05 ポリマテック・ジャパン株式会社 Flexible circuit board and method for manufacturing flexible circuit board
JPWO2017169421A1 (en) * 2016-03-29 2019-02-14 積水ポリマテック株式会社 Flexible circuit board and method for manufacturing flexible circuit board

Also Published As

Publication number Publication date
CH638947GA3 (en) 1983-10-31
CH638947B (en)

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