JPS5480662A - Signal stabilizing circuit - Google Patents

Signal stabilizing circuit

Info

Publication number
JPS5480662A
JPS5480662A JP14838777A JP14838777A JPS5480662A JP S5480662 A JPS5480662 A JP S5480662A JP 14838777 A JP14838777 A JP 14838777A JP 14838777 A JP14838777 A JP 14838777A JP S5480662 A JPS5480662 A JP S5480662A
Authority
JP
Japan
Prior art keywords
signal
time
circuit
output
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14838777A
Other languages
Japanese (ja)
Inventor
Kazuhiro Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14838777A priority Critical patent/JPS5480662A/en
Publication of JPS5480662A publication Critical patent/JPS5480662A/en
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To synchronize the asynchronous signal having the signal width shorter than the internal clock period, by taking the logical product between the output signal of the internally synchronized flip flop and the signal delaying the output signal.
CONSTITUTION: When asynchronous input signal 100 is 1, the latch circuit 1 is set to 1 and the internally synchronized FF2 is set to 1 with the leading of the clock signal 106. At this time, if the time in which the signal 101 is 1 is within the preset time of FF2, FF2 is not surely set to 1 and 1 for slight time as unstable output. Further, the signal 102 is delayed with the delay circuit 3 for required time to stabilize the signal 102. Next, the signals 102 and 103 are inputted to the NAND circuit 4, resetting the latch circuit 1, and the signals 102 and 103 are wave-shaped via the AND circuit 5, causing the internal synchronizing signal 105 where transient unstable signal is removed. Accordingly, one type of clock signal only is used and the internal synchronizing signal is produced with minimum delay time.
COPYRIGHT: (C)1979,JPO&Japio
JP14838777A 1977-12-09 1977-12-09 Signal stabilizing circuit Pending JPS5480662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14838777A JPS5480662A (en) 1977-12-09 1977-12-09 Signal stabilizing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14838777A JPS5480662A (en) 1977-12-09 1977-12-09 Signal stabilizing circuit

Publications (1)

Publication Number Publication Date
JPS5480662A true JPS5480662A (en) 1979-06-27

Family

ID=15451623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14838777A Pending JPS5480662A (en) 1977-12-09 1977-12-09 Signal stabilizing circuit

Country Status (1)

Country Link
JP (1) JPS5480662A (en)

Similar Documents

Publication Publication Date Title
ES430489A1 (en) Synchronizing circuit including two flip-flops and circuit means to protect a synchronized signal from an unstable state of the flip-flops
JPS5797751A (en) Circuit for adding artificial synchronizing signal
JPS5480662A (en) Signal stabilizing circuit
JPS5435666A (en) Timing extraction system
JPS5611528A (en) Switching control circuit of different period clock
JPS5335464A (en) Main and subordinate flip flop circuit
JPS57170688A (en) Jitter compensation circuit
JPS5274246A (en) Skew correcting circuit
JPS57112129A (en) Latch circuit
JPS5679524A (en) Conversion circuit for duty cycle
JPS55146618A (en) Data synchronizing circuit
JPS5571390A (en) Clock stabilizing circuit
JPS5212868A (en) Automatic synchronizing signal generating circuit
JPS5616925A (en) Control system for clock switching
JPS5488168A (en) Phase shift detector
JPS5286758A (en) High accurate digital delay circuit
JPS5689156A (en) Repeater for digital communication
JPS5662448A (en) Synchronizing circuit for asynchronous signal
JPS524811A (en) Pulse demodulator
JPS55676A (en) Pulse delay circuit
JPS5592025A (en) Synchronizing pulse generation circuit
JPS531450A (en) Coder
JPS5250657A (en) Timing output generation circuit
JPS52155935A (en) Synchronous system
JPS5216144A (en) Digital synchronous clock generator