JPS5479017A - Sector clock generating system - Google Patents

Sector clock generating system

Info

Publication number
JPS5479017A
JPS5479017A JP14606577A JP14606577A JPS5479017A JP S5479017 A JPS5479017 A JP S5479017A JP 14606577 A JP14606577 A JP 14606577A JP 14606577 A JP14606577 A JP 14606577A JP S5479017 A JPS5479017 A JP S5479017A
Authority
JP
Japan
Prior art keywords
sector
pulse
phase
clocks
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14606577A
Other languages
Japanese (ja)
Other versions
JPS6113305B2 (en
Inventor
Yoshio Yugawa
Toru Murai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14606577A priority Critical patent/JPS5479017A/en
Publication of JPS5479017A publication Critical patent/JPS5479017A/en
Publication of JPS6113305B2 publication Critical patent/JPS6113305B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To obtain sector clocks of high reliability against noise, peak shift, etc. by discriminating the phase inversion of all "1" by the phase-locked clocks synchronized to clock tracks.
CONSTITUTION: When the "0" sector part (high pulse) of clock track output 14 comes to a phase inversion discriminator 23, it inverts at the rise of phase-locked clocks and a high pulse S1 generates in the Q output. At this time, a counter distributor 27 is set by an initial set pulse and inputs a high pulse S7 to an AND gate G1. Since the Q output of the discriminator 23 is also high pulse, a low pulse is inputted to the terminal R of an even counter 24 to become high clear. Then the counter starts counting of the phase-locked clocks and when the inversion of this continues more than 4 bits, the 22 outputs produce a high pulse S3 and a sector clock generator 28 generates a sector clock. Thereby, the sector clocks of high reliability against noise, peak shift may be obtained.
COPYRIGHT: (C)1979,JPO&Japio
JP14606577A 1977-12-07 1977-12-07 Sector clock generating system Granted JPS5479017A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14606577A JPS5479017A (en) 1977-12-07 1977-12-07 Sector clock generating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14606577A JPS5479017A (en) 1977-12-07 1977-12-07 Sector clock generating system

Publications (2)

Publication Number Publication Date
JPS5479017A true JPS5479017A (en) 1979-06-23
JPS6113305B2 JPS6113305B2 (en) 1986-04-12

Family

ID=15399279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14606577A Granted JPS5479017A (en) 1977-12-07 1977-12-07 Sector clock generating system

Country Status (1)

Country Link
JP (1) JPS5479017A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413267A (en) * 1987-07-06 1989-01-18 Csk Corp Read circuit for optical recording medium
JPS6413266A (en) * 1987-07-06 1989-01-18 Csk Corp Optical recording medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6413267A (en) * 1987-07-06 1989-01-18 Csk Corp Read circuit for optical recording medium
JPS6413266A (en) * 1987-07-06 1989-01-18 Csk Corp Optical recording medium

Also Published As

Publication number Publication date
JPS6113305B2 (en) 1986-04-12

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