JPS5477506A - Disturbance signal suppression circuit for fm radio receiver - Google Patents
Disturbance signal suppression circuit for fm radio receiverInfo
- Publication number
- JPS5477506A JPS5477506A JP14528177A JP14528177A JPS5477506A JP S5477506 A JPS5477506 A JP S5477506A JP 14528177 A JP14528177 A JP 14528177A JP 14528177 A JP14528177 A JP 14528177A JP S5477506 A JPS5477506 A JP S5477506A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- disturbance
- disturbance signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001629 suppression Effects 0.000 title abstract 2
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
- H03G3/345—Muting during a short period of time when noise pulses are detected, i.e. blanking
Landscapes
- Noise Elimination (AREA)
Abstract
PURPOSE:To ensure the effective suppression of the disturbance signal by controlling the frequency bands of the disturbance signals in accordance with the reception field. CONSTITUTION:The output of tuner 1 is introduced to the field intensity detecting circuit to obtain the control signal corresponding to the input field or the tuning condition. With this control signal, the active frequency band of circuit 6' which detects the disturbance signal from the output of FM detector 2 is controlled to be widen when the reception level is high and to be narrowed when the reception level is low respectively. And the control signal is generated from circuit 6' when the disturbance signal is detected to control gate 4. Thus, the output of delay amplifier circuit 3 is prevented from being supplied to output circuit 5. In this case, the signal given from signal holding circuit 8 is supplied to output circuit 5.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14528177A JPS5477506A (en) | 1977-12-02 | 1977-12-02 | Disturbance signal suppression circuit for fm radio receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14528177A JPS5477506A (en) | 1977-12-02 | 1977-12-02 | Disturbance signal suppression circuit for fm radio receiver |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5477506A true JPS5477506A (en) | 1979-06-21 |
JPS5614011B2 JPS5614011B2 (en) | 1981-04-01 |
Family
ID=15381501
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14528177A Granted JPS5477506A (en) | 1977-12-02 | 1977-12-02 | Disturbance signal suppression circuit for fm radio receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5477506A (en) |
-
1977
- 1977-12-02 JP JP14528177A patent/JPS5477506A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5614011B2 (en) | 1981-04-01 |
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