JPS5464437A - Data transfer control system - Google Patents

Data transfer control system

Info

Publication number
JPS5464437A
JPS5464437A JP13056077A JP13056077A JPS5464437A JP S5464437 A JPS5464437 A JP S5464437A JP 13056077 A JP13056077 A JP 13056077A JP 13056077 A JP13056077 A JP 13056077A JP S5464437 A JPS5464437 A JP S5464437A
Authority
JP
Japan
Prior art keywords
buffer
transmission data
channel
control system
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13056077A
Other languages
Japanese (ja)
Other versions
JPS5719459B2 (en
Inventor
Tomohito Shibata
Tadaaki Imai
Kazuo Shimomichi
Kanzo Noda
Masaaki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13056077A priority Critical patent/JPS5464437A/en
Publication of JPS5464437A publication Critical patent/JPS5464437A/en
Publication of JPS5719459B2 publication Critical patent/JPS5719459B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To avoid unnecessary processing of line control channel at the application of power supply, by providing the conditional display means of the transmission data buffer to the line adaptor.
CONSTITUTION: The conditional display means 8 of the transmission data buffer 15 is provided in the line adaptor 3, and the line control channel 1, after confirming the vacancy of the buffer 15 with the output of the means 8, supplied transmission data to the buffer 15. Further, the means 8 uses flag bit which is set when data is written in the buffer 15 and reset with the interrupt reception signal from the channel 1, and delivers the interrupt signal to the channel 1 when the flag bit is set and the buffer 15 is vacant.
COPYRIGHT: (C)1979,JPO&Japio
JP13056077A 1977-10-31 1977-10-31 Data transfer control system Granted JPS5464437A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13056077A JPS5464437A (en) 1977-10-31 1977-10-31 Data transfer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13056077A JPS5464437A (en) 1977-10-31 1977-10-31 Data transfer control system

Publications (2)

Publication Number Publication Date
JPS5464437A true JPS5464437A (en) 1979-05-24
JPS5719459B2 JPS5719459B2 (en) 1982-04-22

Family

ID=15037167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13056077A Granted JPS5464437A (en) 1977-10-31 1977-10-31 Data transfer control system

Country Status (1)

Country Link
JP (1) JPS5464437A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271556A (en) * 1985-05-28 1986-12-01 Oki Electric Ind Co Ltd Direct memory access system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51107733A (en) * 1975-02-18 1976-09-24 Motorola Inc
JPS5255451A (en) * 1975-10-30 1977-05-06 Motorola Inc Digital device for synchronous data communication

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51107733A (en) * 1975-02-18 1976-09-24 Motorola Inc
JPS5255451A (en) * 1975-10-30 1977-05-06 Motorola Inc Digital device for synchronous data communication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61271556A (en) * 1985-05-28 1986-12-01 Oki Electric Ind Co Ltd Direct memory access system

Also Published As

Publication number Publication date
JPS5719459B2 (en) 1982-04-22

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