JPS5451305A - Synchronizer for sampling frequency - Google Patents

Synchronizer for sampling frequency

Info

Publication number
JPS5451305A
JPS5451305A JP11761377A JP11761377A JPS5451305A JP S5451305 A JPS5451305 A JP S5451305A JP 11761377 A JP11761377 A JP 11761377A JP 11761377 A JP11761377 A JP 11761377A JP S5451305 A JPS5451305 A JP S5451305A
Authority
JP
Japan
Prior art keywords
clock frequency
transmission
sampling
reception
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11761377A
Other languages
Japanese (ja)
Other versions
JPS6130456B2 (en
Inventor
Kazumoto Iinuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP11761377A priority Critical patent/JPS5451305A/en
Publication of JPS5451305A publication Critical patent/JPS5451305A/en
Publication of JPS6130456B2 publication Critical patent/JPS6130456B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Time-Division Multiplex Systems (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Television Systems (AREA)

Abstract

PURPOSE: To synchronize a sampling frequency with any transmission line clock frequency by transmitting information for the synchronization between sampling frequencies at the transmission side and reception side regardless of the data frame of a transmission line.
CONSTITUTION: At the transmission side, the 1st comparing method 5 compares transmission sampling clock frequency (fs) with transmisstion-line clock frequency (fe) to obtain the relation between (fs) and (fe) as relative information ΔS, which is transmitted together with other information to transmission line 10 vial buffer memory 7. At the reception side, on the other hand, relative information ΔS is detected 18, and the 2nd comparing method 15 compares reception clock frequency (fR) with transmisstion-line clock frequency (fe)to obtain the relation between (fR) and (fe) as relative information ΔR. Then, reception sampling frequency (fR) is so controlled that relative information ΔS will agree with ΔR
COPYRIGHT: (C)1979,JPO&Japio
JP11761377A 1977-09-29 1977-09-29 Synchronizer for sampling frequency Granted JPS5451305A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11761377A JPS5451305A (en) 1977-09-29 1977-09-29 Synchronizer for sampling frequency

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11761377A JPS5451305A (en) 1977-09-29 1977-09-29 Synchronizer for sampling frequency

Publications (2)

Publication Number Publication Date
JPS5451305A true JPS5451305A (en) 1979-04-23
JPS6130456B2 JPS6130456B2 (en) 1986-07-14

Family

ID=14716083

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11761377A Granted JPS5451305A (en) 1977-09-29 1977-09-29 Synchronizer for sampling frequency

Country Status (1)

Country Link
JP (1) JPS5451305A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6449496A (en) * 1987-08-20 1989-02-23 Nec Corp System for controlling sampling clock phase
US5289508A (en) * 1990-11-30 1994-02-22 Fujitsu Limited Clock information transmitting device and clock information receiving device
US5519835A (en) * 1990-12-20 1996-05-21 Fujitsu Limited Method and apparatus for controlling the flow of data transmissions by generating a succession of ready signals to a high-performance parallel interface(HIPPI) terminal connected to a broadband integrated services digital network (B-ISDN)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0436783Y2 (en) * 1986-07-18 1992-08-31

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6449496A (en) * 1987-08-20 1989-02-23 Nec Corp System for controlling sampling clock phase
US5289508A (en) * 1990-11-30 1994-02-22 Fujitsu Limited Clock information transmitting device and clock information receiving device
US5519835A (en) * 1990-12-20 1996-05-21 Fujitsu Limited Method and apparatus for controlling the flow of data transmissions by generating a succession of ready signals to a high-performance parallel interface(HIPPI) terminal connected to a broadband integrated services digital network (B-ISDN)
US5710942A (en) * 1990-12-20 1998-01-20 Fujitsu Limited Adapter monitoring storage capacity of its buffer and sequentially generating ready signals to notify a terminal to transfer more burst data to the buffer

Also Published As

Publication number Publication date
JPS6130456B2 (en) 1986-07-14

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