JPS54162909A - Line signal control system - Google Patents

Line signal control system

Info

Publication number
JPS54162909A
JPS54162909A JP7161578A JP7161578A JPS54162909A JP S54162909 A JPS54162909 A JP S54162909A JP 7161578 A JP7161578 A JP 7161578A JP 7161578 A JP7161578 A JP 7161578A JP S54162909 A JPS54162909 A JP S54162909A
Authority
JP
Japan
Prior art keywords
signal
line
transmits
circuit
line signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7161578A
Other languages
Japanese (ja)
Inventor
Yusuke Ogata
Toshio Katsuki
Yujiro Sasahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7161578A priority Critical patent/JPS54162909A/en
Publication of JPS54162909A publication Critical patent/JPS54162909A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)

Abstract

PURPOSE:To perform the transfer of line signals before lapse of the recognition time of the line signal in order to shorten the transfer signal at the multi-step repeating exchange from the preceding to next circuit or vice versa. CONSTITUTION:Receiver 51 within signal unit 5 transmits line signal F1 or F2 sent from the next circuit to central controller CC via scan circuit 7, and also transmits signal SP1 and SP2 in the same way if the line signal continues more than the fixed time T1 and T2. Controller CC, when receiving signal SP1, transmits immediately transmission command SF1 or SF2 of signal F1 or F2 to the transmitter similar to transmitter 52. Thus the transmitter transmits the line signals. With reception of signal SP2, CC recognizes that the line signal is effective to continue the transmission of the line signals to the preceding circuit. However, in case the line signal is not effective, the transmission of the line signals to the preceding circuit is stopped immediately.
JP7161578A 1978-06-14 1978-06-14 Line signal control system Pending JPS54162909A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7161578A JPS54162909A (en) 1978-06-14 1978-06-14 Line signal control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7161578A JPS54162909A (en) 1978-06-14 1978-06-14 Line signal control system

Publications (1)

Publication Number Publication Date
JPS54162909A true JPS54162909A (en) 1979-12-25

Family

ID=13465721

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7161578A Pending JPS54162909A (en) 1978-06-14 1978-06-14 Line signal control system

Country Status (1)

Country Link
JP (1) JPS54162909A (en)

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