JPS54156484A - Non-volatile semiconductor memory device - Google Patents

Non-volatile semiconductor memory device

Info

Publication number
JPS54156484A
JPS54156484A JP6525278A JP6525278A JPS54156484A JP S54156484 A JPS54156484 A JP S54156484A JP 6525278 A JP6525278 A JP 6525278A JP 6525278 A JP6525278 A JP 6525278A JP S54156484 A JPS54156484 A JP S54156484A
Authority
JP
Japan
Prior art keywords
electrode
self
alignment
phosphorus
added
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6525278A
Other languages
Japanese (ja)
Inventor
Masanori Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6525278A priority Critical patent/JPS54156484A/en
Publication of JPS54156484A publication Critical patent/JPS54156484A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
    • H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To increase gm, by placing the high concentration region of the same type as the substrate to a part of the source or drain layer with self-alignment, covering the floating gate electrode locally with this region, and determining a part of the shape with self-alignment to the control gate electrode. CONSTITUTION:On the gate oxide film 4 on the P<-> type Si substrate 1, the control electrode 7 of phosphorus added polycrystal Si is placed via the floating gate electrode 5 of phosphorus added polycrystal Si and second gate oxide film 6. The electrode 5 is determined for the shape with self-alignment partly to the electrode 7, and the ends are in agreement. The P layer 8 is provided with self-alignment by B ion injection, by taking the electrode as a mask, phosphorus is added with self- alignment to form the N<+> layers 9 and 10. Next, the electrodes 13 and 14 are attached with selective open window. Since the hot carrier injection is located near the drain, it is not necessary to coat the overall channel by the electrode 5, the area of the electrode 5 is taken small, the threshold voltage is changed greater, and further, the channel part opposing to the electrode 6 directly obtains greater conductiviry with the control voltage than others, to form the memrory device excellent in performance.
JP6525278A 1978-05-30 1978-05-30 Non-volatile semiconductor memory device Pending JPS54156484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6525278A JPS54156484A (en) 1978-05-30 1978-05-30 Non-volatile semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6525278A JPS54156484A (en) 1978-05-30 1978-05-30 Non-volatile semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS54156484A true JPS54156484A (en) 1979-12-10

Family

ID=13281518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6525278A Pending JPS54156484A (en) 1978-05-30 1978-05-30 Non-volatile semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS54156484A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4597000A (en) * 1981-10-19 1986-06-24 Itt Industries, Inc. Floating-gate memory cell
US4868619A (en) * 1984-11-21 1989-09-19 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US4894692A (en) * 1987-06-03 1990-01-16 Mitsubishi Denki Kabushiki Kaisha MESFET with alpha particle protection
JPH034567A (en) * 1989-06-01 1991-01-10 Toshiba Corp Semiconductor memory device
US5021847A (en) * 1984-05-15 1991-06-04 Waferscale Integration, Inc. Split gate memory array having staggered floating gate rows and method for making same
US5117269A (en) * 1989-03-09 1992-05-26 Sgs-Thomson Microelectronics S.R.L. Eprom memory array with crosspoint configuration
US5216269A (en) * 1989-03-31 1993-06-01 U.S. Philips Corp. Electrically-programmable semiconductor memories with buried injector region

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4597000A (en) * 1981-10-19 1986-06-24 Itt Industries, Inc. Floating-gate memory cell
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
US5021847A (en) * 1984-05-15 1991-06-04 Waferscale Integration, Inc. Split gate memory array having staggered floating gate rows and method for making same
US4868619A (en) * 1984-11-21 1989-09-19 Exel Microelectronics, Inc. Single transistor electrically programmable memory device and method
US4894692A (en) * 1987-06-03 1990-01-16 Mitsubishi Denki Kabushiki Kaisha MESFET with alpha particle protection
US5117269A (en) * 1989-03-09 1992-05-26 Sgs-Thomson Microelectronics S.R.L. Eprom memory array with crosspoint configuration
US5216269A (en) * 1989-03-31 1993-06-01 U.S. Philips Corp. Electrically-programmable semiconductor memories with buried injector region
JPH034567A (en) * 1989-06-01 1991-01-10 Toshiba Corp Semiconductor memory device

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