JPS54153543A - Interruption system between processors - Google Patents
Interruption system between processorsInfo
- Publication number
- JPS54153543A JPS54153543A JP6167678A JP6167678A JPS54153543A JP S54153543 A JPS54153543 A JP S54153543A JP 6167678 A JP6167678 A JP 6167678A JP 6167678 A JP6167678 A JP 6167678A JP S54153543 A JPS54153543 A JP S54153543A
- Authority
- JP
- Japan
- Prior art keywords
- interruption
- processor
- address
- memory unit
- main memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Multi Processors (AREA)
- Bus Control (AREA)
Abstract
PURPOSE: To perform the interruption control between processors suitable for a microcomputer, by assigning the memory area of a part of the main memory unit in common use with each processor by one address each as the interruption request generation part corresponding to each processor.
CONSTITUTION: The interruption is made by writing in the interruption request pattern to the address of the main memory unit M assigned to the interruption request generation part IM2 corresponding to the interrupted processor (e.g. P2) from the processor requesting the interruption (e.g. P1), by means of the memory write instruction. Further, in case of interruption release, it is made by writing in the interruption release pattern to the address of the main memory unit M assigned to the interruption request generating part (e.g. IM2) to be released, by means of the memory write instruction.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6167678A JPS54153543A (en) | 1978-05-25 | 1978-05-25 | Interruption system between processors |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6167678A JPS54153543A (en) | 1978-05-25 | 1978-05-25 | Interruption system between processors |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54153543A true JPS54153543A (en) | 1979-12-03 |
Family
ID=13178083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6167678A Pending JPS54153543A (en) | 1978-05-25 | 1978-05-25 | Interruption system between processors |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54153543A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58500145A (en) * | 1981-01-15 | 1983-01-20 | ハリス・コ−ポレイシヨン | Interrupt concatenation and monitoring system |
JPS5897758A (en) * | 1981-12-04 | 1983-06-10 | Matsushita Electric Ind Co Ltd | Controlling system of shared memory |
WO1985005709A1 (en) * | 1984-06-05 | 1985-12-19 | Fanuc Ltd | Method of sending and receiving data |
JPS63271654A (en) * | 1987-04-30 | 1988-11-09 | Yokogawa Medical Syst Ltd | Multiprocessor system |
JPS63292362A (en) * | 1987-05-26 | 1988-11-29 | Fujitsu Ltd | Inter-system communication control system |
JPS6478360A (en) * | 1988-08-04 | 1989-03-23 | Nec Corp | Information processor |
JPH06195308A (en) * | 1988-07-26 | 1994-07-15 | Ishikawajima Harima Heavy Ind Co Ltd | Inter-computer transmission method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50115732A (en) * | 1974-02-22 | 1975-09-10 | ||
JPS5267931A (en) * | 1975-12-04 | 1977-06-06 | Toshiba Corp | Control system for multi-processor system |
-
1978
- 1978-05-25 JP JP6167678A patent/JPS54153543A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50115732A (en) * | 1974-02-22 | 1975-09-10 | ||
JPS5267931A (en) * | 1975-12-04 | 1977-06-06 | Toshiba Corp | Control system for multi-processor system |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58500145A (en) * | 1981-01-15 | 1983-01-20 | ハリス・コ−ポレイシヨン | Interrupt concatenation and monitoring system |
JPS5897758A (en) * | 1981-12-04 | 1983-06-10 | Matsushita Electric Ind Co Ltd | Controlling system of shared memory |
WO1985005709A1 (en) * | 1984-06-05 | 1985-12-19 | Fanuc Ltd | Method of sending and receiving data |
JPS63271654A (en) * | 1987-04-30 | 1988-11-09 | Yokogawa Medical Syst Ltd | Multiprocessor system |
JPS63292362A (en) * | 1987-05-26 | 1988-11-29 | Fujitsu Ltd | Inter-system communication control system |
JPH06195308A (en) * | 1988-07-26 | 1994-07-15 | Ishikawajima Harima Heavy Ind Co Ltd | Inter-computer transmission method |
JPS6478360A (en) * | 1988-08-04 | 1989-03-23 | Nec Corp | Information processor |
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