JPS54146935A - Mask programmable read/write memory - Google Patents

Mask programmable read/write memory

Info

Publication number
JPS54146935A
JPS54146935A JP5576778A JP5576778A JPS54146935A JP S54146935 A JPS54146935 A JP S54146935A JP 5576778 A JP5576778 A JP 5576778A JP 5576778 A JP5576778 A JP 5576778A JP S54146935 A JPS54146935 A JP S54146935A
Authority
JP
Japan
Prior art keywords
memory cell
contents
programmable read
write memory
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5576778A
Other languages
Japanese (ja)
Inventor
Kazuhide Kawada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5576778A priority Critical patent/JPS54146935A/en
Publication of JPS54146935A publication Critical patent/JPS54146935A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To make it possible to rewrite contents of an arbitrary address as required after holding contents, which are designated previously after power supply, by making a memory cell unbalanced intentionally. CONSTITUTION:A flip flop formed by connecting two stages of amplifier circuits including transistor Q1 or Q2 is defined as a memory cell, and transistor Q3 which operates as the transfer gate for reading contents of this memory cell or writing data in this memory cell is provided. Then, the memory cell is made unbalanced by setting the ratio of load resistances R1 and R2 to a value other than 1 or using transistors of different electrical characteristics as Q1 and Q2 or combining these methods, and the memory cell is set to a prescribed state by power supply.
JP5576778A 1978-05-10 1978-05-10 Mask programmable read/write memory Pending JPS54146935A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5576778A JPS54146935A (en) 1978-05-10 1978-05-10 Mask programmable read/write memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5576778A JPS54146935A (en) 1978-05-10 1978-05-10 Mask programmable read/write memory

Publications (1)

Publication Number Publication Date
JPS54146935A true JPS54146935A (en) 1979-11-16

Family

ID=13008006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5576778A Pending JPS54146935A (en) 1978-05-10 1978-05-10 Mask programmable read/write memory

Country Status (1)

Country Link
JP (1) JPS54146935A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3032333A1 (en) 1980-08-27 1982-04-22 Siemens AG, 1000 Berlin und 8000 München MONOLITHIC STATIC STORAGE CELL AND METHOD FOR THEIR OPERATION
JPS5845697A (en) * 1981-09-08 1983-03-16 インテル・コ−ポレ−シヨン Non-volatile memory
US4418401A (en) * 1982-12-29 1983-11-29 Ibm Corporation Latent image ram cell
EP0250930A2 (en) * 1986-07-01 1988-01-07 International Business Machines Corporation Multiple ROM data state, read/write memory cell
EP0344894A2 (en) * 1988-06-02 1989-12-06 Xilinx, Inc. Memory cell
EP0460691A2 (en) * 1990-06-08 1991-12-11 Kabushiki Kaisha Toshiba Semiconductor memory cell
JP2013229097A (en) * 2012-04-26 2013-11-07 Gn Resound As Semiconductor memory with similar ram and rom cells

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3032333A1 (en) 1980-08-27 1982-04-22 Siemens AG, 1000 Berlin und 8000 München MONOLITHIC STATIC STORAGE CELL AND METHOD FOR THEIR OPERATION
US4396996A (en) * 1980-08-27 1983-08-02 Siemens Aktiengesellschaft Monolithic static memory cell and method for its operation
JPS5845697A (en) * 1981-09-08 1983-03-16 インテル・コ−ポレ−シヨン Non-volatile memory
US4418401A (en) * 1982-12-29 1983-11-29 Ibm Corporation Latent image ram cell
EP0250930A2 (en) * 1986-07-01 1988-01-07 International Business Machines Corporation Multiple ROM data state, read/write memory cell
EP0344894A2 (en) * 1988-06-02 1989-12-06 Xilinx, Inc. Memory cell
EP0460691A2 (en) * 1990-06-08 1991-12-11 Kabushiki Kaisha Toshiba Semiconductor memory cell
US5311464A (en) * 1990-06-08 1994-05-10 Kabushiki Kaisha Toshiba Semiconductor memory cell farming a ROM cell from a RAM cell
JP2013229097A (en) * 2012-04-26 2013-11-07 Gn Resound As Semiconductor memory with similar ram and rom cells
US8964456B2 (en) 2012-04-26 2015-02-24 Gn Resound A/S Semiconductor memory with similar RAM and ROM cells

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