JPS54142065A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS54142065A
JPS54142065A JP5086078A JP5086078A JPS54142065A JP S54142065 A JPS54142065 A JP S54142065A JP 5086078 A JP5086078 A JP 5086078A JP 5086078 A JP5086078 A JP 5086078A JP S54142065 A JPS54142065 A JP S54142065A
Authority
JP
Japan
Prior art keywords
semiconductor device
print substrate
adhesive
outer frame
wiring layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5086078A
Other languages
Japanese (ja)
Inventor
Keiji Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5086078A priority Critical patent/JPS54142065A/en
Publication of JPS54142065A publication Critical patent/JPS54142065A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To increase the working efficiency by applying the adhesive to part of the outer frame of the semiconductor device.
CONSTITUTION: Adhesive 2 is sticked on the back of outer frame 1 of the semiconductor device, and the device is fixed temporarily to print substrate 5. Then external lead 3 is positioned to wiring layer 4. Under these conditions, the device is made to pass through the solder soaking tank. Thus, the wiring layer is soldered to the external lead, and at the same time the semiconductor device is fixed permanently to the print substrate. With this method, the adhesive coating is omitted in the process under which the semiconductor device is fixed temporarily to the print substrate. Thus, the device insertion can be simplified, increasing the working efficiency.
COPYRIGHT: (C)1979,JPO&Japio
JP5086078A 1978-04-27 1978-04-27 Semiconductor device Pending JPS54142065A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5086078A JPS54142065A (en) 1978-04-27 1978-04-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5086078A JPS54142065A (en) 1978-04-27 1978-04-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS54142065A true JPS54142065A (en) 1979-11-05

Family

ID=12870467

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5086078A Pending JPS54142065A (en) 1978-04-27 1978-04-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS54142065A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017511609A (en) * 2014-04-18 2017-04-20 レイセオン カンパニー Method for aligning surface mount packages for thermal improvement

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS496462A (en) * 1972-05-10 1974-01-21

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS496462A (en) * 1972-05-10 1974-01-21

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017511609A (en) * 2014-04-18 2017-04-20 レイセオン カンパニー Method for aligning surface mount packages for thermal improvement

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