JPS54140407A - Time slot conversion system for time-division switch device - Google Patents
Time slot conversion system for time-division switch deviceInfo
- Publication number
- JPS54140407A JPS54140407A JP4764778A JP4764778A JPS54140407A JP S54140407 A JPS54140407 A JP S54140407A JP 4764778 A JP4764778 A JP 4764778A JP 4764778 A JP4764778 A JP 4764778A JP S54140407 A JPS54140407 A JP S54140407A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- buffer memory
- address
- signal
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Time-Division Multiplex Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To prevent the signals within one frame from being transmitted to the different frames by providing two units of the buffer memory between the multiplication circuit and the distribution circuit and then inverting the memories every frame period. CONSTITUTION:Two unit of buffer memory 21 and 22 are provided between multiplication circuit 10 and distribution circuit 80. For control memory 30 which has one turn with every frame, the information designating address m of buffer memory A21 and address m of buffer memory B22 are written into the addresses of time slot number ti and tj respectively. The designation of buffer memory A and B are inverted every frame period through the inverting means. For the incomingside highway signal, signal ti of frame O is written into address m of A21 and then read out after being carried over to frame 1. While signal tj of frame O is written into address m of B21 and then read out at frame 1. In this way, signal ti and tj withing one frame are transmitted to the same frame.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4764778A JPS54140407A (en) | 1978-04-24 | 1978-04-24 | Time slot conversion system for time-division switch device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4764778A JPS54140407A (en) | 1978-04-24 | 1978-04-24 | Time slot conversion system for time-division switch device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54140407A true JPS54140407A (en) | 1979-10-31 |
Family
ID=12781033
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4764778A Pending JPS54140407A (en) | 1978-04-24 | 1978-04-24 | Time slot conversion system for time-division switch device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54140407A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4972407A (en) * | 1988-10-03 | 1990-11-20 | Fujitsu Limited | Time-division switching circuit transforming data formats |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49106209A (en) * | 1973-02-08 | 1974-10-08 | ||
JPS5255406A (en) * | 1975-10-31 | 1977-05-06 | Fujitsu Ltd | Memory switch system |
-
1978
- 1978-04-24 JP JP4764778A patent/JPS54140407A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS49106209A (en) * | 1973-02-08 | 1974-10-08 | ||
JPS5255406A (en) * | 1975-10-31 | 1977-05-06 | Fujitsu Ltd | Memory switch system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4972407A (en) * | 1988-10-03 | 1990-11-20 | Fujitsu Limited | Time-division switching circuit transforming data formats |
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