JPS5413742A - Arithmetic circuit - Google Patents

Arithmetic circuit

Info

Publication number
JPS5413742A
JPS5413742A JP7934477A JP7934477A JPS5413742A JP S5413742 A JPS5413742 A JP S5413742A JP 7934477 A JP7934477 A JP 7934477A JP 7934477 A JP7934477 A JP 7934477A JP S5413742 A JPS5413742 A JP S5413742A
Authority
JP
Japan
Prior art keywords
arithmetic circuit
group
arithmetic
detector
detects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7934477A
Other languages
Japanese (ja)
Inventor
Takao Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7934477A priority Critical patent/JPS5413742A/en
Publication of JPS5413742A publication Critical patent/JPS5413742A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/5052—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination using carry completion detection, either over all stages or at sample stages only

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)

Abstract

PURPOSE:To control an arithmetic time depending upon the result of a detector, which detects the operation state of each group of arithmetic units, provided to each group.
JP7934477A 1977-07-01 1977-07-01 Arithmetic circuit Pending JPS5413742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7934477A JPS5413742A (en) 1977-07-01 1977-07-01 Arithmetic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7934477A JPS5413742A (en) 1977-07-01 1977-07-01 Arithmetic circuit

Publications (1)

Publication Number Publication Date
JPS5413742A true JPS5413742A (en) 1979-02-01

Family

ID=13687276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7934477A Pending JPS5413742A (en) 1977-07-01 1977-07-01 Arithmetic circuit

Country Status (1)

Country Link
JP (1) JPS5413742A (en)

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