JPS54129317A - Omit phase detecting circuit of converter - Google Patents

Abstract

PURPOSE: To detect an omit phase of a gate pulse given to a converter speedily and indifferently an operation frequency by detecting an omit phase at a time point when a current shifting voltage of thyristors becomes to negative.

CONSTITUTION: A curren shifting voltage of U phase SCR 11 becomes to R - T phase, the signal is converted to a logical signal at a level detecting circuit 21, becomes to a set signal of FF 23 through a pulsing circuit 22 and makes Q output as a Logic "1" at a time point when a current shifting voltage of R - T phase becomes positive. When U phase gate pulse becomes a reset signal of FF 23, Q output becomes to a logic "0" and inputs to AND 25, however as a signal from an inverter circuit 24 is also input, an input signal becomes to a logic "0" as long as a gate pulse to SCR 11 is existing. Accordingly when a gate pulse becomes not existing even when a current shifting voltage becomes to negative as Q output of FF 23 remains as a logic "1", both inputs to a circuit 25 become logics "0" therefore a logic "1" is output and at this time point an omit phase can be detected.

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