JPS54127644A - Code conversion system - Google Patents

Code conversion system

Info

Publication number
JPS54127644A
JPS54127644A JP3572578A JP3572578A JPS54127644A JP S54127644 A JPS54127644 A JP S54127644A JP 3572578 A JP3572578 A JP 3572578A JP 3572578 A JP3572578 A JP 3572578A JP S54127644 A JPS54127644 A JP S54127644A
Authority
JP
Japan
Prior art keywords
bits
information
code
foul
bit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3572578A
Other languages
Japanese (ja)
Inventor
Yoshikazu Kazuma
Hirotaka Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3572578A priority Critical patent/JPS54127644A/en
Publication of JPS54127644A publication Critical patent/JPS54127644A/en
Pending legal-status Critical Current

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To secure the code conversion with the memory element featuring a small bit number of the memory address as well as with a small number of the memory element by providing the memory element by two steps for the code conversion.
CONSTITUTION: With supply 1 of the coded information to the HOLLERITH code of 12 bits, memory element C detects the foul code as well as three bits of the information corresponding to the memory address of seven bits from bit 1 to 7 which are the specified bits in information 1. And the result is delivered by one bit, and memory element B16 and 17 deliver the information by four bits corresponding to the memory address of eight bits. In case "1" of more than one bits exists in the input of bit 1 to 7 supplied to element C, the input information is the foul code. Thus, abnormal information 19 is delivered to the information processor from element C. In this way, the foul code is detected individually with no foul code detection element and then can be delivered in the form of the abnormal information.
COPYRIGHT: (C)1979,JPO&Japio
JP3572578A 1978-03-28 1978-03-28 Code conversion system Pending JPS54127644A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3572578A JPS54127644A (en) 1978-03-28 1978-03-28 Code conversion system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3572578A JPS54127644A (en) 1978-03-28 1978-03-28 Code conversion system

Publications (1)

Publication Number Publication Date
JPS54127644A true JPS54127644A (en) 1979-10-03

Family

ID=12449819

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3572578A Pending JPS54127644A (en) 1978-03-28 1978-03-28 Code conversion system

Country Status (1)

Country Link
JP (1) JPS54127644A (en)

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