JPS54125939A - Bus line control method - Google Patents

Bus line control method

Info

Publication number
JPS54125939A
JPS54125939A JP3311878A JP3311878A JPS54125939A JP S54125939 A JPS54125939 A JP S54125939A JP 3311878 A JP3311878 A JP 3311878A JP 3311878 A JP3311878 A JP 3311878A JP S54125939 A JPS54125939 A JP S54125939A
Authority
JP
Japan
Prior art keywords
bus
cpu1
reset signal
collective
retrieving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3311878A
Other languages
Japanese (ja)
Inventor
Nobuo Tomita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3311878A priority Critical patent/JPS54125939A/en
Publication of JPS54125939A publication Critical patent/JPS54125939A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To ensure an effective control for the bus line when the collective reset is given, by retrieving all I/OS' occupied by the processor and then transmitting the collective reset signals to the retrieved I/O in sequence.
CONSTITUTION: In case CPU1-1 occupies the using right of I/O5-1 on shared I/O bus 7 and carries out the control, the collective reset signal is transmitted from CPU1-1 by some reason to discontinue all processes under execution and to secure the original state. In such case, the resetting is possible easily to I/O2-1 within the self-system. For I/O5-1 on bus 7, however, bus coupler 4-2 which caught the reset signal from CPU1-1 takes the acquisition sequence for the bus using right of bus 7 to obtain the bus using right, and then CPU1-1 gives a sequential retrieving to I/O5-1 which is under occupation. After this, CPU1-1 reads out I/O recognition information DUA under occupation to decode it, and then the reset signal line exclusive for the retrieved shared I/O is driven.
COPYRIGHT: (C)1979,JPO&Japio
JP3311878A 1978-03-24 1978-03-24 Bus line control method Pending JPS54125939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3311878A JPS54125939A (en) 1978-03-24 1978-03-24 Bus line control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3311878A JPS54125939A (en) 1978-03-24 1978-03-24 Bus line control method

Publications (1)

Publication Number Publication Date
JPS54125939A true JPS54125939A (en) 1979-09-29

Family

ID=12377708

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3311878A Pending JPS54125939A (en) 1978-03-24 1978-03-24 Bus line control method

Country Status (1)

Country Link
JP (1) JPS54125939A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263326A (en) * 1985-09-12 1987-03-20 Nec Corp Emergency controlling system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263326A (en) * 1985-09-12 1987-03-20 Nec Corp Emergency controlling system

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