JPS54123864A - Programmable logic array - Google Patents

Programmable logic array

Info

Publication number
JPS54123864A
JPS54123864A JP3134078A JP3134078A JPS54123864A JP S54123864 A JPS54123864 A JP S54123864A JP 3134078 A JP3134078 A JP 3134078A JP 3134078 A JP3134078 A JP 3134078A JP S54123864 A JPS54123864 A JP S54123864A
Authority
JP
Japan
Prior art keywords
line
output
signal
logical
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3134078A
Other languages
Japanese (ja)
Inventor
Masaaki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3134078A priority Critical patent/JPS54123864A/en
Publication of JPS54123864A publication Critical patent/JPS54123864A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain the programmable logic array easy for inspection, by providing the selection section which outputs the logical product signal selected with the control signal at inspection and the AND array section taking the logical product of result from the interpretation circuit of the input signal. CONSTITUTION:When the logical value 1 is given from the control signal 35 to the decoder circuit section 30, the output line of the decoder 37 is at logical value 1 for one line according to the state of the input signal 36. When the signal 35 is 0, the output line 38 from the decoder 37 is into one state at the same time. Thus, the output of the circuit 37 is programmed so that the product item line 40 is exclusively selected at each cross point 39 of the AND array section 32. To the decoder circuit 31, only the input signal 41 is given and the output line 43 is at logical value 1 for one line according to the state of the signal 41. In the output 43, at each cross point 44 of the array 32, the logical product of the desired input signal is given on the product item line. The logical product signal from the line 40 is programmed so that the logical sum is obtained on the sum item line 46 at each cross point 45 of the OR array 33 and output is made from the output hold circut 34.
JP3134078A 1978-03-17 1978-03-17 Programmable logic array Pending JPS54123864A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3134078A JPS54123864A (en) 1978-03-17 1978-03-17 Programmable logic array

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3134078A JPS54123864A (en) 1978-03-17 1978-03-17 Programmable logic array

Publications (1)

Publication Number Publication Date
JPS54123864A true JPS54123864A (en) 1979-09-26

Family

ID=12328501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3134078A Pending JPS54123864A (en) 1978-03-17 1978-03-17 Programmable logic array

Country Status (1)

Country Link
JP (1) JPS54123864A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818902A (en) * 1985-12-09 1989-04-04 Nixdorf Computer Ag Integrated circuit component

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4871546A (en) * 1971-12-27 1973-09-27

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4871546A (en) * 1971-12-27 1973-09-27

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4818902A (en) * 1985-12-09 1989-04-04 Nixdorf Computer Ag Integrated circuit component

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