JPS54114056A - Ternary logic circuit - Google Patents

Ternary logic circuit

Info

Publication number
JPS54114056A
JPS54114056A JP2137478A JP2137478A JPS54114056A JP S54114056 A JPS54114056 A JP S54114056A JP 2137478 A JP2137478 A JP 2137478A JP 2137478 A JP2137478 A JP 2137478A JP S54114056 A JPS54114056 A JP S54114056A
Authority
JP
Japan
Prior art keywords
circuit
inverter
power voltage
level
giving
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2137478A
Other languages
Japanese (ja)
Other versions
JPS59175B2 (en
Inventor
Takao Naya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Original Assignee
Tokyo Sanyo Electric Co Ltd
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Sanyo Electric Co Ltd, Sanyo Electric Co Ltd filed Critical Tokyo Sanyo Electric Co Ltd
Priority to JP53021374A priority Critical patent/JPS59175B2/en
Publication of JPS54114056A publication Critical patent/JPS54114056A/en
Publication of JPS59175B2 publication Critical patent/JPS59175B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To secure the steady inversion of the power voltage from 1/2 level through the full level of the power voltage by varying the inverter characteristics of the inverter circuit comprising by giving the continuous connection to plural inverter devices in response to the output of the input circuit. CONSTITUTION:Input circuit 1 sets the high, intermediate and low levels. And inverter circuit 2 reverses at the intermediate level or less, and inverter circuit 3 is inverted at the intermediate level or more. Here, circuit 3 is constituted by giving the continuous connection to inverter devices 31-33, and circuit 2 and 3 are formed with the enhancement-type MOS transistor of the conducting channel. Then the inverter characteristics is varied in response to the output of circuit 1. As a result, inverter circuit 3 which features the steady inversion between 1/2VDD and VDD of power voltage VDD can be obtained in an easy way.
JP53021374A 1978-02-24 1978-02-24 ternary logic circuit Expired JPS59175B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53021374A JPS59175B2 (en) 1978-02-24 1978-02-24 ternary logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53021374A JPS59175B2 (en) 1978-02-24 1978-02-24 ternary logic circuit

Publications (2)

Publication Number Publication Date
JPS54114056A true JPS54114056A (en) 1979-09-05
JPS59175B2 JPS59175B2 (en) 1984-01-05

Family

ID=12053312

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53021374A Expired JPS59175B2 (en) 1978-02-24 1978-02-24 ternary logic circuit

Country Status (1)

Country Link
JP (1) JPS59175B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100524A (en) * 1980-01-17 1981-08-12 Matsushita Electric Works Ltd Reset/counter test mode switching circuit of electronic timer
JPS56164631A (en) * 1980-05-22 1981-12-17 Toshiba Corp Signal line precharging circuit
JPS5871732A (en) * 1981-10-02 1983-04-28 フエアチァイルド　カメラ　アンド　インストルメント　コ−ポレ−ション Try level input buffer
JPS59151530A (en) * 1983-02-10 1984-08-30 Toshiba Corp Semiconductor integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56100524A (en) * 1980-01-17 1981-08-12 Matsushita Electric Works Ltd Reset/counter test mode switching circuit of electronic timer
JPS56164631A (en) * 1980-05-22 1981-12-17 Toshiba Corp Signal line precharging circuit
JPS5871732A (en) * 1981-10-02 1983-04-28 フエアチァイルド　カメラ　アンド　インストルメント　コ−ポレ−ション Try level input buffer
JPH0380373B2 (en) * 1981-10-02 1991-12-24 Fueachairudo Kamera Endo Insutsurumento Corp
JPS59151530A (en) * 1983-02-10 1984-08-30 Toshiba Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS59175B2 (en) 1984-01-05

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