JPS54106137A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS54106137A
JPS54106137A JP1316378A JP1316378A JPS54106137A JP S54106137 A JPS54106137 A JP S54106137A JP 1316378 A JP1316378 A JP 1316378A JP 1316378 A JP1316378 A JP 1316378A JP S54106137 A JPS54106137 A JP S54106137A
Authority
JP
Japan
Prior art keywords
chip selection
line array
chip
high level
array wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1316378A
Other languages
Japanese (ja)
Inventor
Toshio Hayashi
Kuniyasu Kawarada
Masao Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP1316378A priority Critical patent/JPS54106137A/en
Publication of JPS54106137A publication Critical patent/JPS54106137A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Landscapes

  • Static Random-Access Memory (AREA)

Abstract

PURPOSE:To increase the chip selection access time by connecting the current switching transistor to the other end of the line array wire of the matrix formation of the semiconductor cell and then applying the signals synchronized with the chip selection signals. CONSTITUTION:The emitter of current switching Tr10 is connected to the other end of line array wire 6, and signal VCS is applied to the base in synchronization with the chip selection signal. Signal VCS is at a high level at the chip selection time, and all of Tr10 are turned off. At the chip non-selection time, signal VCS becomes high level, and driving circuit 5 of the line array wire which was at a low level at the chip selection time is turned off with Tr10 turned on. And circuit 5 of the line array wire which was at a high level at the chip selection time is kept at the ON-state and Tr10 kept OFF. After this, the high level of the line array wire is kept as it is when the chip is selected, and the low level is discharged by holding currnt IH. With setting the detection voltage at the detector circuit, the reading becomes possible simultaneously with input of the chip selection signal, thus shortening the chip selection access time.
JP1316378A 1978-02-08 1978-02-08 Semiconductor memory device Pending JPS54106137A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1316378A JPS54106137A (en) 1978-02-08 1978-02-08 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1316378A JPS54106137A (en) 1978-02-08 1978-02-08 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS54106137A true JPS54106137A (en) 1979-08-20

Family

ID=11825493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1316378A Pending JPS54106137A (en) 1978-02-08 1978-02-08 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS54106137A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0050037A2 (en) * 1980-10-15 1982-04-21 Fujitsu Limited Semiconductor memory device
JPS5938994A (en) * 1982-08-27 1984-03-03 Hitachi Ltd Semiconductor memory driving circuit
JPS6080195A (en) * 1983-10-07 1985-05-08 Fujitsu Ltd Semiconductor memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0050037A2 (en) * 1980-10-15 1982-04-21 Fujitsu Limited Semiconductor memory device
JPS5938994A (en) * 1982-08-27 1984-03-03 Hitachi Ltd Semiconductor memory driving circuit
JPS6080195A (en) * 1983-10-07 1985-05-08 Fujitsu Ltd Semiconductor memory
JPH0318273B2 (en) * 1983-10-07 1991-03-12 Fujitsu Ltd

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