JPS54105934A - Input/output channel device - Google Patents

Input/output channel device

Info

Publication number
JPS54105934A
JPS54105934A JP1241078A JP1241078A JPS54105934A JP S54105934 A JPS54105934 A JP S54105934A JP 1241078 A JP1241078 A JP 1241078A JP 1241078 A JP1241078 A JP 1241078A JP S54105934 A JPS54105934 A JP S54105934A
Authority
JP
Japan
Prior art keywords
input
request
state information
information request
data request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1241078A
Other languages
Japanese (ja)
Inventor
Hiroshi Osaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1241078A priority Critical patent/JPS54105934A/en
Publication of JPS54105934A publication Critical patent/JPS54105934A/en
Pending legal-status Critical Current

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  • Information Transfer Systems (AREA)

Abstract

PURPOSE: To ensure detection of the request of the input/output device without monopolizing the common interface by providing the individual data request line and the state information request line between input/output devices.
CONSTITUTION: Input/output channel device 1 receives the state information request from each of input/output devices 20W2n via corresponding state information request lines 30W3n and also receives the data request through corresponding data request lines 40W4n. In such constitution, the reception of the state information request and the data request is preformed by the hardware of device 1 in perfect parallel to memorization 15 and 19 of the input/output device numbers and setting of interruption FF14 and 11. As a result, common input interface 50 is not monopolized, and furthermore the request accepting procedure required so far can be omitted.
COPYRIGHT: (C)1979,JPO&Japio
JP1241078A 1978-02-08 1978-02-08 Input/output channel device Pending JPS54105934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1241078A JPS54105934A (en) 1978-02-08 1978-02-08 Input/output channel device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1241078A JPS54105934A (en) 1978-02-08 1978-02-08 Input/output channel device

Publications (1)

Publication Number Publication Date
JPS54105934A true JPS54105934A (en) 1979-08-20

Family

ID=11804481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1241078A Pending JPS54105934A (en) 1978-02-08 1978-02-08 Input/output channel device

Country Status (1)

Country Link
JP (1) JPS54105934A (en)

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