JPS5390827A - Memory access system - Google Patents

Memory access system

Info

Publication number
JPS5390827A
JPS5390827A JP560777A JP560777A JPS5390827A JP S5390827 A JPS5390827 A JP S5390827A JP 560777 A JP560777 A JP 560777A JP 560777 A JP560777 A JP 560777A JP S5390827 A JPS5390827 A JP S5390827A
Authority
JP
Japan
Prior art keywords
address
memory access
access system
odd
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP560777A
Other languages
Japanese (ja)
Inventor
Hiroshi Sakurai
Hidekazu Nabeshima
Hiroyoshi Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NITSUKIYOU DENKI KOGYO KK
Toshiba Corp
Original Assignee
NITSUKIYOU DENKI KOGYO KK
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NITSUKIYOU DENKI KOGYO KK, Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical NITSUKIYOU DENKI KOGYO KK
Priority to JP560777A priority Critical patent/JPS5390827A/en
Publication of JPS5390827A publication Critical patent/JPS5390827A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

PURPOSE:To carry out the data process for the odd address and the odd length against the program which is given no adjustment for the address and the length yet, by deciding the memory assigned address is the odd address or the even address when the memory address is assigned.
JP560777A 1977-01-21 1977-01-21 Memory access system Pending JPS5390827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP560777A JPS5390827A (en) 1977-01-21 1977-01-21 Memory access system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP560777A JPS5390827A (en) 1977-01-21 1977-01-21 Memory access system

Publications (1)

Publication Number Publication Date
JPS5390827A true JPS5390827A (en) 1978-08-10

Family

ID=11615882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP560777A Pending JPS5390827A (en) 1977-01-21 1977-01-21 Memory access system

Country Status (1)

Country Link
JP (1) JPS5390827A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63196967A (en) * 1987-02-10 1988-08-15 Fujitsu Ltd Data transfer control equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63196967A (en) * 1987-02-10 1988-08-15 Fujitsu Ltd Data transfer control equipment

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