JPS5371555A - Digital mixer - Google Patents

Digital mixer

Info

Publication number
JPS5371555A
JPS5371555A JP14651076A JP14651076A JPS5371555A JP S5371555 A JPS5371555 A JP S5371555A JP 14651076 A JP14651076 A JP 14651076A JP 14651076 A JP14651076 A JP 14651076A JP S5371555 A JPS5371555 A JP S5371555A
Authority
JP
Japan
Prior art keywords
signals
digital mixer
input
input terminals
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14651076A
Other languages
Japanese (ja)
Other versions
JPS6041485B2 (en
Inventor
Makoto Furuhata
Michinao Osawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP51146510A priority Critical patent/JPS6041485B2/en
Publication of JPS5371555A publication Critical patent/JPS5371555A/en
Publication of JPS6041485B2 publication Critical patent/JPS6041485B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/64—Generators producing trains of pulses, i.e. finite sequences of pulses
    • H03K3/72—Generators producing trains of pulses, i.e. finite sequences of pulses with means for varying repetition rate of trains

Landscapes

  • Manipulation Of Pulses (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:Two input signals are applied to the 1st input terminals of the 1st and 2nd NAND circuits respectively, and delay signals of the inversion NOR output of the two input signals are applied to the 2nd input terminals, so that the difference frequency signal of both the signals will be outputted from this FF output terminal.
JP51146510A 1976-12-08 1976-12-08 digital mixer Expired JPS6041485B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51146510A JPS6041485B2 (en) 1976-12-08 1976-12-08 digital mixer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51146510A JPS6041485B2 (en) 1976-12-08 1976-12-08 digital mixer

Publications (2)

Publication Number Publication Date
JPS5371555A true JPS5371555A (en) 1978-06-26
JPS6041485B2 JPS6041485B2 (en) 1985-09-17

Family

ID=15409254

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51146510A Expired JPS6041485B2 (en) 1976-12-08 1976-12-08 digital mixer

Country Status (1)

Country Link
JP (1) JPS6041485B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5857176U (en) * 1981-10-13 1983-04-18 ソニー株式会社 Frequency difference discrimination circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5857176U (en) * 1981-10-13 1983-04-18 ソニー株式会社 Frequency difference discrimination circuit
JPH0136381Y2 (en) * 1981-10-13 1989-11-06

Also Published As

Publication number Publication date
JPS6041485B2 (en) 1985-09-17

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