JPS5366357A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS5366357A
JPS5366357A JP13564977A JP13564977A JPS5366357A JP S5366357 A JPS5366357 A JP S5366357A JP 13564977 A JP13564977 A JP 13564977A JP 13564977 A JP13564977 A JP 13564977A JP S5366357 A JPS5366357 A JP S5366357A
Authority
JP
Japan
Prior art keywords
logic circuit
reduce
operationable
integration
constitute
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13564977A
Other languages
Japanese (ja)
Other versions
JPS5633900B2 (en
Inventor
Yasoji Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP13564977A priority Critical patent/JPS5366357A/en
Publication of JPS5366357A publication Critical patent/JPS5366357A/en
Publication of JPS5633900B2 publication Critical patent/JPS5633900B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/01—Modifications for accelerating switching
    • H03K19/017—Modifications for accelerating switching in field-effect transistor circuits
    • H03K19/01728—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals
    • H03K19/01742—Modifications for accelerating switching in field-effect transistor circuits in synchronous circuits, i.e. by using clock signals by means of a pull-up or down element

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Shift Register Type Memory (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the number of components in the logic circuit using isolated type FET, to reduce the power consumption, and to constitute the circuit configuration suitable for integration and operationable stably even at lower frequencies.
JP13564977A 1977-11-14 1977-11-14 Logic circuit Granted JPS5366357A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13564977A JPS5366357A (en) 1977-11-14 1977-11-14 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13564977A JPS5366357A (en) 1977-11-14 1977-11-14 Logic circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP9768272A Division JPS5333017B2 (en) 1972-09-30 1972-09-30

Publications (2)

Publication Number Publication Date
JPS5366357A true JPS5366357A (en) 1978-06-13
JPS5633900B2 JPS5633900B2 (en) 1981-08-06

Family

ID=15156724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13564977A Granted JPS5366357A (en) 1977-11-14 1977-11-14 Logic circuit

Country Status (1)

Country Link
JP (1) JPS5366357A (en)

Also Published As

Publication number Publication date
JPS5633900B2 (en) 1981-08-06

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