JPS5319775A - Large scale integrated circuit - Google Patents

Large scale integrated circuit

Info

Publication number
JPS5319775A
JPS5319775A JP9400376A JP9400376A JPS5319775A JP S5319775 A JPS5319775 A JP S5319775A JP 9400376 A JP9400376 A JP 9400376A JP 9400376 A JP9400376 A JP 9400376A JP S5319775 A JPS5319775 A JP S5319775A
Authority
JP
Japan
Prior art keywords
integrated circuit
large scale
scale integrated
edges
forbidden region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9400376A
Other languages
Japanese (ja)
Inventor
Ryotaro Kamikawai
Yutaka Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9400376A priority Critical patent/JPS5319775A/en
Publication of JPS5319775A publication Critical patent/JPS5319775A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0207Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:Designing of conductor patterns for the purpose of intercircuit connection is facilitated by so disposing the input and output points of the rows along the mutually parallel opposing two edges of the wiring forbidden region of a large scale integrated circuit that these points are off the same lines perpendicular to the edges of the wiring forbidden region.
JP9400376A 1976-08-09 1976-08-09 Large scale integrated circuit Pending JPS5319775A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9400376A JPS5319775A (en) 1976-08-09 1976-08-09 Large scale integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9400376A JPS5319775A (en) 1976-08-09 1976-08-09 Large scale integrated circuit

Publications (1)

Publication Number Publication Date
JPS5319775A true JPS5319775A (en) 1978-02-23

Family

ID=14098233

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9400376A Pending JPS5319775A (en) 1976-08-09 1976-08-09 Large scale integrated circuit

Country Status (1)

Country Link
JP (1) JPS5319775A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432085A (en) * 1977-08-16 1979-03-09 Mitsubishi Electric Corp Semiconductor intergrated circuit
JPS54147788A (en) * 1978-05-11 1979-11-19 Mitsubishi Electric Corp Semiconductor device of master slice system
JPS55162947U (en) * 1979-05-10 1980-11-22
EP0405460A2 (en) * 1989-06-26 1991-01-02 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5432085A (en) * 1977-08-16 1979-03-09 Mitsubishi Electric Corp Semiconductor intergrated circuit
JPS6329826B2 (en) * 1977-08-16 1988-06-15 Mitsubishi Electric Corp
JPS54147788A (en) * 1978-05-11 1979-11-19 Mitsubishi Electric Corp Semiconductor device of master slice system
JPS6330783B2 (en) * 1978-05-11 1988-06-21 Mitsubishi Electric Corp
JPS55162947U (en) * 1979-05-10 1980-11-22
EP0405460A2 (en) * 1989-06-26 1991-01-02 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system
US5111271A (en) * 1989-06-26 1992-05-05 Kabushiki Kaisha Toshiba Semiconductor device using standard cell system

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