JPS53125709A - Agc circuit - Google Patents

Agc circuit

Info

Publication number
JPS53125709A
JPS53125709A JP4085577A JP4085577A JPS53125709A JP S53125709 A JPS53125709 A JP S53125709A JP 4085577 A JP4085577 A JP 4085577A JP 4085577 A JP4085577 A JP 4085577A JP S53125709 A JPS53125709 A JP S53125709A
Authority
JP
Japan
Prior art keywords
agc circuit
gain
circuit
interferring
deteriorating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4085577A
Other languages
Japanese (ja)
Inventor
Akira Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4085577A priority Critical patent/JPS53125709A/en
Publication of JPS53125709A publication Critical patent/JPS53125709A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/3052—Automatic control in amplifiers having semiconductor devices in bandpass amplifiers (H.F. or I.F.) or in frequency-changers used in a (super)heterodyne receiver
    • H03G3/3068—Circuits generating control signals for both R.F. and I.F. stages

Landscapes

  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To enable to obtain a desirable signal with moderate level without deteriorating the S/N, by decreasing the gain of the RF circuit and increasing the gain of the IF stage depending on levels of interferring waves.
JP4085577A 1977-04-08 1977-04-08 Agc circuit Pending JPS53125709A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4085577A JPS53125709A (en) 1977-04-08 1977-04-08 Agc circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4085577A JPS53125709A (en) 1977-04-08 1977-04-08 Agc circuit

Publications (1)

Publication Number Publication Date
JPS53125709A true JPS53125709A (en) 1978-11-02

Family

ID=12592163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4085577A Pending JPS53125709A (en) 1977-04-08 1977-04-08 Agc circuit

Country Status (1)

Country Link
JP (1) JPS53125709A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016513937A (en) * 2013-03-11 2016-05-16 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Amplifier with inductive degeneration, configurable gain, and input matching

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016513937A (en) * 2013-03-11 2016-05-16 クゥアルコム・インコーポレイテッドＱｕａｌｃｏｍｍ Ｉｎｃｏｒｐｏｒａｔｅｄ Amplifier with inductive degeneration, configurable gain, and input matching

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