JPS5258448A - Delay circuit - Google Patents

Delay circuit

Info

Publication number
JPS5258448A
JPS5258448A JP13409375A JP13409375A JPS5258448A JP S5258448 A JPS5258448 A JP S5258448A JP 13409375 A JP13409375 A JP 13409375A JP 13409375 A JP13409375 A JP 13409375A JP S5258448 A JPS5258448 A JP S5258448A
Authority
JP
Japan
Prior art keywords
delay circuit
consistuting
responding
capacitor
turning
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13409375A
Other languages
Japanese (ja)
Inventor
Koshiro Iwasaki
Junichi Mameta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP13409375A priority Critical patent/JPS5258448A/en
Publication of JPS5258448A publication Critical patent/JPS5258448A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/125—Discriminating pulses
    • H03K5/1252—Suppression or limitation of noise or interference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00293—Output pulse is a delayed pulse issued after a rising or a falling edge, the length of the output pulse not being in relation with the length of the input triggering pulse

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To obtain a delay circuit not responding to shorter pulse by turning on and off by the terminal voltage of a capacitor consistuting a time constant circuit.
JP13409375A 1975-11-10 1975-11-10 Delay circuit Pending JPS5258448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13409375A JPS5258448A (en) 1975-11-10 1975-11-10 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13409375A JPS5258448A (en) 1975-11-10 1975-11-10 Delay circuit

Publications (1)

Publication Number Publication Date
JPS5258448A true JPS5258448A (en) 1977-05-13

Family

ID=15120256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13409375A Pending JPS5258448A (en) 1975-11-10 1975-11-10 Delay circuit

Country Status (1)

Country Link
JP (1) JPS5258448A (en)

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