JPS5255834A - Memory control system - Google Patents
Memory control systemInfo
- Publication number
- JPS5255834A JPS5255834A JP8143876A JP8143876A JPS5255834A JP S5255834 A JPS5255834 A JP S5255834A JP 8143876 A JP8143876 A JP 8143876A JP 8143876 A JP8143876 A JP 8143876A JP S5255834 A JPS5255834 A JP S5255834A
- Authority
- JP
- Japan
- Prior art keywords
- control system
- memory control
- memory
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Multi Processors (AREA)
- Bus Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US59395375A | 1975-07-08 | 1975-07-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5255834A true JPS5255834A (en) | 1977-05-07 |
Family
ID=24376905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8143876A Pending JPS5255834A (en) | 1975-07-08 | 1976-07-08 | Memory control system |
Country Status (4)
Country | Link |
---|---|
JP (1) | JPS5255834A (en) |
CA (1) | CA1062376A (en) |
DE (1) | DE2630711A1 (en) |
FR (1) | FR2325107A1 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2744111A1 (en) * | 1977-09-30 | 1979-04-05 | Siemens Ag | CIRCUIT ARRANGEMENT FOR THE INPUT OF INTERRUPTION COMMANDS AND OUTPUT OF INTERRUPTION CONFIRMATIONS FOR COMPUTER SYSTEMS |
IT1108732B (en) * | 1978-05-05 | 1985-12-09 | Honeywell Inf Systems | BIDIRECTIONAL TRANSMISSION SYSTEM OF INTERLOCKED SIGNALS |
JPS5833770A (en) * | 1981-08-24 | 1983-02-28 | Sony Corp | Program transfer method for digital data |
US4847867A (en) * | 1986-09-01 | 1989-07-11 | Nec Corporation | Serial bus interface system for data communication using two-wire line as clock bus and data bus |
-
1976
- 1976-07-06 CA CA256,436A patent/CA1062376A/en not_active Expired
- 1976-07-08 JP JP8143876A patent/JPS5255834A/en active Pending
- 1976-07-08 FR FR7620850A patent/FR2325107A1/en not_active Withdrawn
- 1976-07-08 DE DE19762630711 patent/DE2630711A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
DE2630711A1 (en) | 1977-10-06 |
CA1062376A (en) | 1979-09-11 |
FR2325107A1 (en) | 1977-04-15 |
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