JPS52104855A - Phase synchronization - Google Patents

Phase synchronization

Info

Publication number
JPS52104855A
JPS52104855A JP2098376A JP2098376A JPS52104855A JP S52104855 A JPS52104855 A JP S52104855A JP 2098376 A JP2098376 A JP 2098376A JP 2098376 A JP2098376 A JP 2098376A JP S52104855 A JPS52104855 A JP S52104855A
Authority
JP
Japan
Prior art keywords
output
phase synchronization
delay
frequency
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2098376A
Other languages
Japanese (ja)
Other versions
JPS6013333B2 (en
Inventor
Tetsuo Soejima
Yoshitaka Hiratsuka
Masao Yamazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP51020983A priority Critical patent/JPS6013333B2/en
Publication of JPS52104855A publication Critical patent/JPS52104855A/en
Publication of JPS6013333B2 publication Critical patent/JPS6013333B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To prepare the delay/advance conditions of phase and reduce an output jitter by so arranging that an input frequency signal provided to one input terminal of delay-type flipflop may be output into an output terminal belatedly by one pulse of an output signal obtained by frequency-dividing an oscillation frequency.
JP51020983A 1976-02-27 1976-02-27 Phase synchronization method Expired JPS6013333B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP51020983A JPS6013333B2 (en) 1976-02-27 1976-02-27 Phase synchronization method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP51020983A JPS6013333B2 (en) 1976-02-27 1976-02-27 Phase synchronization method

Publications (2)

Publication Number Publication Date
JPS52104855A true JPS52104855A (en) 1977-09-02
JPS6013333B2 JPS6013333B2 (en) 1985-04-06

Family

ID=12042378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP51020983A Expired JPS6013333B2 (en) 1976-02-27 1976-02-27 Phase synchronization method

Country Status (1)

Country Link
JP (1) JPS6013333B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214116A (en) * 1984-04-09 1985-10-26 Nagano Nippon Musen Kk Digital type phase control circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4962064A (en) * 1972-10-18 1974-06-15

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4962064A (en) * 1972-10-18 1974-06-15

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60214116A (en) * 1984-04-09 1985-10-26 Nagano Nippon Musen Kk Digital type phase control circuit
JPH0467375B2 (en) * 1984-04-09 1992-10-28 Nagano Nippon Musen Kk

Also Published As

Publication number Publication date
JPS6013333B2 (en) 1985-04-06

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