JPS51147933A - Binary full adder circuit - Google Patents
Binary full adder circuitInfo
- Publication number
- JPS51147933A JPS51147933A JP7179275A JP7179275A JPS51147933A JP S51147933 A JPS51147933 A JP S51147933A JP 7179275 A JP7179275 A JP 7179275A JP 7179275 A JP7179275 A JP 7179275A JP S51147933 A JPS51147933 A JP S51147933A
- Authority
- JP
- Japan
- Prior art keywords
- full adder
- adder circuit
- binary full
- binary
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
- G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Mathematical Optimization (AREA)
- General Engineering & Computer Science (AREA)
Abstract
PURPOSE:To design a higher speed operation of a binary full adder by transmitting a carry through signal through complementary MOS transmitting gates.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7179275A JPS51147933A (en) | 1975-06-13 | 1975-06-13 | Binary full adder circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7179275A JPS51147933A (en) | 1975-06-13 | 1975-06-13 | Binary full adder circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS51147933A true JPS51147933A (en) | 1976-12-18 |
Family
ID=13470765
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7179275A Pending JPS51147933A (en) | 1975-06-13 | 1975-06-13 | Binary full adder circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS51147933A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52116034A (en) * | 1976-02-23 | 1977-09-29 | Intel Corp | Binary adder for adding multiple bit binary number |
JPS53123635A (en) * | 1977-04-05 | 1978-10-28 | Fujitsu Ltd | Sequential carry-type adder |
FR2516675A1 (en) * | 1981-11-19 | 1983-05-20 | Labo Cent Telecommunicat | BINARY ADDITION CELL WITH THREE INPUTS WITH RAPID PROPAGATION OF RETENTION |
JPS59123930A (en) * | 1982-12-29 | 1984-07-17 | Matsushita Electric Ind Co Ltd | Carry signal generator |
JPS59123931A (en) * | 1982-12-29 | 1984-07-17 | Matsushita Electric Ind Co Ltd | Carry signal generator |
JPS6197745A (en) * | 1984-10-17 | 1986-05-16 | Toshiba Corp | Addition circuit |
-
1975
- 1975-06-13 JP JP7179275A patent/JPS51147933A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52116034A (en) * | 1976-02-23 | 1977-09-29 | Intel Corp | Binary adder for adding multiple bit binary number |
JPS5522823B2 (en) * | 1976-02-23 | 1980-06-19 | ||
JPS53123635A (en) * | 1977-04-05 | 1978-10-28 | Fujitsu Ltd | Sequential carry-type adder |
FR2516675A1 (en) * | 1981-11-19 | 1983-05-20 | Labo Cent Telecommunicat | BINARY ADDITION CELL WITH THREE INPUTS WITH RAPID PROPAGATION OF RETENTION |
JPS59123930A (en) * | 1982-12-29 | 1984-07-17 | Matsushita Electric Ind Co Ltd | Carry signal generator |
JPS59123931A (en) * | 1982-12-29 | 1984-07-17 | Matsushita Electric Ind Co Ltd | Carry signal generator |
JPH0218499B2 (en) * | 1982-12-29 | 1990-04-25 | Matsushita Electric Ind Co Ltd | |
JPS6197745A (en) * | 1984-10-17 | 1986-05-16 | Toshiba Corp | Addition circuit |
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