JPS51139286A - Multi-layer wiring pattern - Google Patents

Multi-layer wiring pattern

Info

Publication number
JPS51139286A
JPS51139286A JP6288575A JP6288575A JPS51139286A JP S51139286 A JPS51139286 A JP S51139286A JP 6288575 A JP6288575 A JP 6288575A JP 6288575 A JP6288575 A JP 6288575A JP S51139286 A JPS51139286 A JP S51139286A
Authority
JP
Japan
Prior art keywords
wiring pattern
layer wiring
reduce
wiring
grid
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6288575A
Other languages
Japanese (ja)
Inventor
Ryotaro Kamikawai
Yutaka Harada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6288575A priority Critical patent/JPS51139286A/en
Publication of JPS51139286A publication Critical patent/JPS51139286A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To reduce the interlattice gap of a wiring grid and thereby reduce the area required for the wiring by disposing the center of through-hole intermediate between adjacent grid lattices.
JP6288575A 1975-05-28 1975-05-28 Multi-layer wiring pattern Pending JPS51139286A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6288575A JPS51139286A (en) 1975-05-28 1975-05-28 Multi-layer wiring pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6288575A JPS51139286A (en) 1975-05-28 1975-05-28 Multi-layer wiring pattern

Publications (1)

Publication Number Publication Date
JPS51139286A true JPS51139286A (en) 1976-12-01

Family

ID=13213150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6288575A Pending JPS51139286A (en) 1975-05-28 1975-05-28 Multi-layer wiring pattern

Country Status (1)

Country Link
JP (1) JPS51139286A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61114551A (en) * 1984-11-09 1986-06-02 Toshiba Corp Semiconductor integrated circuit device and pattern layout therefor
JPS63188954A (en) * 1987-01-30 1988-08-04 Nec Corp Programmable logic array device
JPS63188953A (en) * 1987-01-30 1988-08-04 Nec Corp Programmable logic array device
JPS6419739A (en) * 1988-06-24 1989-01-23 Hitachi Ltd Semiconductor integrated circuit device
JPS6427241A (en) * 1988-06-24 1989-01-30 Hitachi Ltd Semiconductor integrated circuit device
JPH01235275A (en) * 1988-03-15 1989-09-20 Seiko Epson Corp Mos semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61114551A (en) * 1984-11-09 1986-06-02 Toshiba Corp Semiconductor integrated circuit device and pattern layout therefor
JPS63188954A (en) * 1987-01-30 1988-08-04 Nec Corp Programmable logic array device
JPS63188953A (en) * 1987-01-30 1988-08-04 Nec Corp Programmable logic array device
JPH01235275A (en) * 1988-03-15 1989-09-20 Seiko Epson Corp Mos semiconductor device
JPS6419739A (en) * 1988-06-24 1989-01-23 Hitachi Ltd Semiconductor integrated circuit device
JPS6427241A (en) * 1988-06-24 1989-01-30 Hitachi Ltd Semiconductor integrated circuit device

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